2 * config-pre.h - common defines for Blackfin boards in config.h
4 * Copyright (c) 2007-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
10 #define __ASM_BLACKFIN_CONFIG_PRE_H__
12 /* Misc helper functions */
13 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
15 /* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
16 * Depending on your cpu, some of these may not be valid, check your HRM.
17 * The actual values here are meaningless as long as they're unique.
19 #define BFIN_BOOT_BYPASS 1 /* bypass bootrom */
20 #define BFIN_BOOT_PARA 2 /* boot ldr out of parallel flash */
21 #define BFIN_BOOT_SPI_MASTER 3 /* boot ldr out of serial flash */
22 #define BFIN_BOOT_SPI_SLAVE 4 /* boot ldr as spi slave */
23 #define BFIN_BOOT_TWI_MASTER 5 /* boot ldr over twi device */
24 #define BFIN_BOOT_TWI_SLAVE 6 /* boot ldr over twi slave */
25 #define BFIN_BOOT_UART 7 /* boot ldr over uart */
26 #define BFIN_BOOT_IDLE 8 /* do nothing, just idle */
27 #define BFIN_BOOT_FIFO 9 /* boot ldr out of FIFO */
28 #define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */
29 #define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */
30 #define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */
31 #define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */
32 #define BFIN_BOOT_RSI_MASTER 14 /* boot ldr from rsi */
33 #define BFIN_BOOT_LP_SLAVE 15 /* boot ldr from link port */
36 static inline const char *get_bfin_boot_mode(int bfin_boot)
39 case BFIN_BOOT_BYPASS: return "bypass";
40 case BFIN_BOOT_PARA: return "parallel flash";
41 case BFIN_BOOT_SPI_MASTER: return "spi flash";
42 case BFIN_BOOT_SPI_SLAVE: return "spi slave";
43 case BFIN_BOOT_TWI_MASTER: return "i2c flash";
44 case BFIN_BOOT_TWI_SLAVE: return "i2c slave";
45 case BFIN_BOOT_UART: return "uart";
46 case BFIN_BOOT_IDLE: return "idle";
47 case BFIN_BOOT_FIFO: return "fifo";
48 case BFIN_BOOT_MEM: return "memory";
49 case BFIN_BOOT_16HOST_DMA: return "16bit dma";
50 case BFIN_BOOT_8HOST_DMA: return "8bit dma";
51 case BFIN_BOOT_NAND: return "nand flash";
52 case BFIN_BOOT_RSI_MASTER: return "rsi master";
53 case BFIN_BOOT_LP_SLAVE: return "link port slave";
54 default: return "INVALID";
59 /* Most bootroms allow for EVT1 redirection */
60 #if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \
61 && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__)
62 # undef CONFIG_BFIN_BOOTROM_USES_EVT1
64 # define CONFIG_BFIN_BOOTROM_USES_EVT1
67 /* Define the default SPI CS used when booting out of SPI */
68 #if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
69 defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
70 defined(__ADSPBF51x__)
71 # define BFIN_BOOT_SPI_SSEL 2
73 # define BFIN_BOOT_SPI_SSEL 1
76 /* Define to get a GPIO CS with the Blackfin SPI controller */
79 /* There is no Blackfin/NetBSD port */
80 #undef CONFIG_BOOTM_NETBSD
82 /* We rarely use interrupts, so favor throughput over latency */
83 #define CONFIG_BFIN_INS_LOWOVERHEAD