3 * Copyright (C) 2012 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
10 #include <asm/blackfin.h>
12 #include <asm/mach-common/bits/pll.h>
13 # define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS)
15 #include <asm/mach-common/bits/cgu.h>
16 # define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
17 # define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
18 # define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
20 # define SSEL_P SYSSEL_P
23 __attribute__((always_inline))
24 static inline uint32_t early_division(uint32_t dividend, uint32_t divisor)
29 for (quotient = 1, i = 1; dividend > divisor; ++i) {
31 if (j > dividend || (j & 0x80000000)) {
34 dividend -= (divisor << i);
42 __attribute__((always_inline))
43 static inline uint32_t early_get_uart_clk(void)
45 uint32_t msel, pll_ctl, vco;
46 uint32_t div, ssel, sclk, uclk;
48 pll_ctl = bfin_read_PLL_CTL();
49 msel = (pll_ctl & MSEL) >> MSEL_P;
51 msel = (MSEL >> MSEL_P) + 1;
53 vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel;
55 if (!pll_is_bypassed()) {
56 div = bfin_read_PLL_DIV();
57 ssel = (div & SSEL) >> SSEL_P;
58 #if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
61 sclk = early_division(vco, ssel);
66 ssel = (div & S0SEL) >> S0SEL_P;
67 uclk = early_division(sclk, ssel);
73 # define get_uart_clk get_sclk0
75 # define get_uart_clk get_sclk