2 * Copyright (C) 2012 Analog Devices Inc.
3 * Licensed under the GPL-2 or later.
9 #include <asm/blackfin.h>
11 #include <asm/mach-common/bits/pll.h>
12 # define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS)
14 #include <asm/mach-common/bits/cgu.h>
15 # define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
16 # define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
17 # define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
19 # define SSEL_P SYSSEL_P
22 __attribute__((always_inline))
23 static inline uint32_t early_division(uint32_t dividend, uint32_t divisor)
28 for (quotient = 1, i = 1; dividend > divisor; ++i) {
30 if (j > dividend || (j & 0x80000000)) {
33 dividend -= (divisor << i);
41 __attribute__((always_inline))
42 static inline uint32_t early_get_uart_clk(void)
44 uint32_t msel, pll_ctl, vco;
45 uint32_t div, ssel, sclk, uclk;
47 pll_ctl = bfin_read_PLL_CTL();
48 msel = (pll_ctl & MSEL) >> MSEL_P;
50 msel = (MSEL >> MSEL_P) + 1;
52 vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel;
54 if (!pll_is_bypassed()) {
55 div = bfin_read_PLL_DIV();
56 ssel = (div & SSEL) >> SSEL_P;
57 #if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
60 sclk = early_division(vco, ssel);
65 ssel = (div & S0SEL) >> S0SEL_P;
66 uclk = early_division(sclk, ssel);
71 extern u_long get_vco(void);
72 extern u_long get_cclk(void);
73 extern u_long get_sclk(void);
76 extern u_long get_sclk0(void);
77 extern u_long get_sclk1(void);
78 extern u_long get_dclk(void);
79 # define get_uart_clk get_sclk0
80 # define get_i2c_clk get_sclk0
81 # define get_spi_clk get_sclk0
83 # define get_uart_clk get_sclk
84 # define get_i2c_clk get_sclk
85 # define get_spi_clk get_sclk