2 * U-boot - serial.c Blackfin Serial Driver
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
7 * BuyWays B.V. (www.buyways.nl)
10 * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
11 * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
12 * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
13 * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
15 * Based on code from 68328 version serial driver imlpementation which was:
16 * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
17 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
18 * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
19 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
21 * (C) Copyright 2000-2004
22 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
24 * Licensed under the GPL-2 or later.
28 * 05000086 - we don't support autobaud
29 * 05000099 - we only use DR bit, so losing others is not a problem
30 * 05000100 - we don't use the UART_IIR register
31 * 05000215 - we poll the uart (no dma/interrupts)
32 * 05000225 - no workaround possible, but this shouldnt cause errors ...
33 * 05000230 - we tweak the baud rate calculation slightly
34 * 05000231 - we always use 1 stop bit
35 * 05000309 - we always enable the uart before we modify it in anyway
36 * 05000350 - we always enable the uart regardless of boot mode
37 * 05000363 - we don't support break signals, so don't generate one
44 #include <linux/compiler.h>
45 #include <asm/blackfin.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 #ifdef CONFIG_UART_CONSOLE
53 #ifdef CONFIG_DEBUG_SERIAL
54 static uart_lsr_t cached_lsr[256];
55 static uart_lsr_t cached_rbr[256];
56 static size_t cache_count;
58 /* The LSR is read-to-clear on some parts, so we have to make sure status
59 * bits aren't inadvertently lost when doing various tests. This also
60 * works around anomaly 05000099 at the same time by keeping a cumulative
61 * tally of all the status bits.
63 static uart_lsr_t uart_lsr_save;
64 static uart_lsr_t uart_lsr_read(uint32_t uart_base)
66 uart_lsr_t lsr = _lsr_read(pUART);
67 uart_lsr_save |= (lsr & (OE|PE|FE|BI));
68 return lsr | uart_lsr_save;
70 /* Just do the clear for everyone since it can't hurt. */
71 static void uart_lsr_clear(uint32_t uart_base)
74 _lsr_write(pUART, -1);
77 /* When debugging is disabled, we only care about the DR bit, so if other
78 * bits get set/cleared, we don't really care since we don't read them
79 * anyways (and thus anomaly 05000099 is irrelevant).
81 static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
83 return _lsr_read(pUART);
85 static void uart_lsr_clear(uint32_t uart_base)
87 _lsr_write(pUART, -1);
91 static void uart_putc(uint32_t uart_base, const char c)
93 /* send a \r for compatibility */
99 /* wait for the hardware fifo to clear up */
100 while (!(uart_lsr_read(uart_base) & THRE))
103 /* queue the character for transmission */
104 bfin_write(&pUART->thr, c);
110 static int uart_tstc(uint32_t uart_base)
113 return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
116 static int uart_getc(uint32_t uart_base)
118 uint16_t uart_rbr_val;
120 /* wait for data ! */
121 while (!uart_tstc(uart_base))
124 /* grab the new byte */
125 uart_rbr_val = bfin_read(&pUART->rbr);
127 #ifdef CONFIG_DEBUG_SERIAL
128 /* grab & clear the LSR */
129 uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
131 cached_lsr[cache_count] = uart_lsr_val;
132 cached_rbr[cache_count] = uart_rbr_val;
133 cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
135 if (uart_lsr_val & (OE|PE|FE|BI)) {
136 printf("\n[SERIAL ERROR]\n");
139 printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
140 cached_rbr[cache_count], cached_lsr[cache_count]);
141 } while (cache_count > 0);
145 uart_lsr_clear(uart_base);
150 #if CONFIG_POST & CONFIG_SYS_POST_UART
156 #if BFIN_UART_HW_VER < 4
159 static void uart_loop(uint32_t uart_base, int state)
163 /* Drain the TX fifo first so bytes don't come back */
164 while (!(uart_lsr_read(uart_base) & TEMT))
167 mcr = bfin_read(&pUART->mcr);
169 mcr |= LOOP_ENA | MRTS;
171 mcr &= ~(LOOP_ENA | MRTS);
172 bfin_write(&pUART->mcr, mcr);
179 static void uart_loop(uint32_t uart_base, int state)
183 /* Drain the TX fifo first so bytes don't come back */
184 while (!(uart_lsr_read(uart_base) & TEMT))
187 control = bfin_read(&pUART->control);
189 control |= LOOP_ENA | MRTS;
191 control &= ~(LOOP_ENA | MRTS);
192 bfin_write(&pUART->control, control);
198 #ifdef CONFIG_SYS_BFIN_UART
200 static void uart_puts(uint32_t uart_base, const char *s)
203 uart_putc(uart_base, *s++);
206 #define DECL_BFIN_UART(n) \
207 static int uart##n##_init(void) \
209 const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
210 peripheral_request_list(pins, "bfin-uart"); \
211 uart_init(MMR_UART(n)); \
212 serial_early_set_baud(MMR_UART(n), gd->baudrate); \
213 uart_lsr_clear(MMR_UART(n)); \
217 static int uart##n##_uninit(void) \
219 return serial_early_uninit(MMR_UART(n)); \
222 static void uart##n##_setbrg(void) \
224 serial_early_set_baud(MMR_UART(n), gd->baudrate); \
227 static int uart##n##_getc(void) \
229 return uart_getc(MMR_UART(n)); \
232 static int uart##n##_tstc(void) \
234 return uart_tstc(MMR_UART(n)); \
237 static void uart##n##_putc(const char c) \
239 uart_putc(MMR_UART(n), c); \
242 static void uart##n##_puts(const char *s) \
244 uart_puts(MMR_UART(n), s); \
248 static void uart##n##_loop(int state) \
250 uart_loop(MMR_UART(n), state); \
254 struct serial_device bfin_serial##n##_device = { \
255 .name = "bfin_uart"#n, \
256 .start = uart##n##_init, \
257 .stop = uart##n##_uninit, \
258 .setbrg = uart##n##_setbrg, \
259 .getc = uart##n##_getc, \
260 .tstc = uart##n##_tstc, \
261 .putc = uart##n##_putc, \
262 .puts = uart##n##_puts, \
263 LOOP(.loop = uart##n##_loop) \
279 __weak struct serial_device *default_serial_console(void)
281 #if CONFIG_UART_CONSOLE == 0
282 return &bfin_serial0_device;
283 #elif CONFIG_UART_CONSOLE == 1
284 return &bfin_serial1_device;
285 #elif CONFIG_UART_CONSOLE == 2
286 return &bfin_serial2_device;
287 #elif CONFIG_UART_CONSOLE == 3
288 return &bfin_serial3_device;
292 void bfin_serial_initialize(void)
295 serial_register(&bfin_serial0_device);
298 serial_register(&bfin_serial1_device);
301 serial_register(&bfin_serial2_device);
304 serial_register(&bfin_serial3_device);
310 /* Symbol for our assembly to call. */
311 void serial_set_baud(uint32_t baud)
313 serial_early_set_baud(UART_BASE, baud);
316 /* Symbol for common u-boot code to call.
317 * Setup the baudrate (brg: baudrate generator).
319 void serial_setbrg(void)
321 serial_set_baud(gd->baudrate);
324 /* Symbol for our assembly to call. */
325 void serial_initialize(void)
327 serial_early_init(UART_BASE);
330 /* Symbol for common u-boot code to call. */
331 int serial_init(void)
335 uart_lsr_clear(UART_BASE);
339 int serial_tstc(void)
341 return uart_tstc(UART_BASE);
344 int serial_getc(void)
346 return uart_getc(UART_BASE);
349 void serial_putc(const char c)
351 uart_putc(UART_BASE, c);
354 void serial_puts(const char *s)
361 void serial_loop(int state)
363 uart_loop(UART_BASE, state);