2 * Code for early processor initialization
4 * Copyright (c) 2004-2011 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #ifndef __BFIN_INITCODE_H__
10 #define __BFIN_INITCODE_H__
12 #include <asm/mach-common/bits/bootrom.h>
14 #ifndef BFIN_IN_INITCODE
15 # define serial_putc(c)
20 #ifndef CONFIG_EBIU_RSTCTL_VAL
21 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
23 #if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
24 # error invalid EBIU_RSTCTL value: must not set reserved bits
27 #ifndef CONFIG_EBIU_MBSCTL_VAL
28 # define CONFIG_EBIU_MBSCTL_VAL 0
31 #if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
32 # error invalid EBIU_DDRQUE value: must not set reserved bits
35 #endif /* __ADSPBF60x__ */
37 __attribute__((always_inline)) static inline void
38 program_async_controller(ADI_BOOT_DATA *bs)
40 #ifdef BFIN_IN_INITCODE
42 * We really only need to setup the async banks early if we're
43 * booting out of it. Otherwise, do it later on in cpu_init.
45 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS &&
46 CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA)
53 /* Program the async banks controller. */
55 bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
56 bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
57 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
62 /* Not all parts have these additional MMRs. */
64 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
67 # ifdef CONFIG_EBIU_MODE_VAL
68 bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
70 # ifdef CONFIG_EBIU_FCTL_VAL
71 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
77 #else /* __ADSPBF60x__ */
78 /* Program the static memory controller. */
79 # ifdef CONFIG_SMC_GCTL_VAL
80 bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
82 # ifdef CONFIG_SMC_B0CTL_VAL
83 bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
85 # ifdef CONFIG_SMC_B0TIM_VAL
86 bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
88 # ifdef CONFIG_SMC_B0ETIM_VAL
89 bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
91 # ifdef CONFIG_SMC_B1CTL_VAL
92 bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
94 # ifdef CONFIG_SMC_B1TIM_VAL
95 bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
97 # ifdef CONFIG_SMC_B1ETIM_VAL
98 bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
100 # ifdef CONFIG_SMC_B2CTL_VAL
101 bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
103 # ifdef CONFIG_SMC_B2TIM_VAL
104 bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
106 # ifdef CONFIG_SMC_B2ETIM_VAL
107 bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
109 # ifdef CONFIG_SMC_B3CTL_VAL
110 bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
112 # ifdef CONFIG_SMC_B3TIM_VAL
113 bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
115 # ifdef CONFIG_SMC_B3ETIM_VAL
116 bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);