2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
7 * Copyright (c) 2004-2011 Analog Devices Inc.
9 * Licensed under the GPL-2 or later.
12 #define BFIN_IN_INITCODE
15 #include <asm/blackfin.h>
16 #include <asm/mach-common/bits/bootrom.h>
17 #include <asm/mach-common/bits/core.h>
18 #include <asm/mach-common/bits/ebiu.h>
19 #include <asm/mach-common/bits/pll.h>
20 #include <asm/mach-common/bits/uart.h>
24 __attribute__((always_inline))
25 static inline void serial_init(void)
27 uint32_t uart_base = UART_DLL;
30 # ifdef BFIN_BOOT_UART_USE_RTS
31 # define BFIN_UART_USE_RTS 1
33 # define BFIN_UART_USE_RTS 0
35 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
38 /* force RTS rather than relying on auto RTS */
39 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
41 /* Wait for the line to clear up. We cannot rely on UART
42 * registers as none of them reflect the status of the RSR.
43 * Instead, we'll sleep for ~10 bit times at 9600 baud.
44 * We can precalc things here by assuming boot values for
45 * PLL rather than loading registers and calculating.
46 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
48 * Divisor = (SCLK / baud) / 16
49 * SCLK = baud * 16 * Divisor
50 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
51 * CCLK = (16 * Divisor * 5) * (9600 / 10)
52 * In reality, this will probably be just about 1 second delay,
53 * so assuming 9600 baud is OK (both as a very low and too high
54 * speed as this will buffer things enough).
56 #define _NUMBITS (10) /* how many bits to delay */
57 #define _LOWBAUD (9600) /* low baud rate */
58 #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
59 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
60 #define _NUMINS (3) /* how many instructions in loop */
61 #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
64 asm volatile("" : : : "memory");
68 if (BFIN_DEBUG_EARLY_SERIAL) {
69 int ucen = bfin_read16(&pUART->gctl) & UCEN;
70 serial_early_init(uart_base);
72 /* If the UART is off, that means we need to program
73 * the baud rate ourselves initially.
76 serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
80 __attribute__((always_inline))
81 static inline void serial_deinit(void)
84 uint32_t uart_base = UART_DLL;
86 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
87 /* clear forced RTS rather than relying on auto RTS */
88 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
93 __attribute__((always_inline))
94 static inline void serial_putc(char c)
96 uint32_t uart_base = UART_DLL;
98 if (!BFIN_DEBUG_EARLY_SERIAL)
104 bfin_write16(&pUART->thr, c);
106 while (!(bfin_read16(&pUART->lsr) & TEMT))
110 #include "initcode.h"
112 __attribute__((always_inline)) static inline void
113 program_nmi_handler(void)
117 /* Older bootroms don't create a dummy NMI handler,
118 * so make one ourselves ASAP in case it fires.
120 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
124 "%0 = RETS;" /* Save current RETS */
125 "CALL 1f;" /* Figure out current PC */
126 "RTN;" /* The simple NMI handler */
128 "%1 = RETS;" /* Load addr of NMI handler */
129 "RETS = %0;" /* Restore RETS */
130 "[%2] = %1;" /* Write NMI handler */
131 : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
135 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
136 * us a freq of 16MHz for SPI which should generally be
137 * slow enough for the slow reads the bootrom uses.
139 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
140 ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
141 (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
142 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
144 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
146 #ifndef CONFIG_SPI_BAUD_INITBLOCK
147 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
150 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
153 /* PLL_DIV defines */
154 #ifndef CONFIG_PLL_DIV_VAL
155 # if (CONFIG_CCLK_DIV == 1)
156 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
157 # elif (CONFIG_CCLK_DIV == 2)
158 # define CONFIG_CCLK_ACT_DIV CCLK_DIV2
159 # elif (CONFIG_CCLK_DIV == 4)
160 # define CONFIG_CCLK_ACT_DIV CCLK_DIV4
161 # elif (CONFIG_CCLK_DIV == 8)
162 # define CONFIG_CCLK_ACT_DIV CCLK_DIV8
164 # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
166 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
169 #ifndef CONFIG_PLL_LOCKCNT_VAL
170 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
173 #ifndef CONFIG_PLL_CTL_VAL
174 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
177 /* Make sure our voltage value is sane so we don't blow up! */
178 #ifndef CONFIG_VR_CTL_VAL
179 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
180 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
181 # define CCLK_VLEV_120 400000000
182 # define CCLK_VLEV_125 533000000
183 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
184 # define CCLK_VLEV_120 401000000
185 # define CCLK_VLEV_125 401000000
186 # elif defined(__ADSPBF561__)
187 # define CCLK_VLEV_120 300000000
188 # define CCLK_VLEV_125 501000000
190 # if BFIN_CCLK < CCLK_VLEV_120
191 # define CONFIG_VR_CTL_VLEV VLEV_120
192 # elif BFIN_CCLK < CCLK_VLEV_125
193 # define CONFIG_VR_CTL_VLEV VLEV_125
195 # define CONFIG_VR_CTL_VLEV VLEV_130
197 # if defined(__ADSPBF52x__) /* TBD; use default */
198 # undef CONFIG_VR_CTL_VLEV
199 # define CONFIG_VR_CTL_VLEV VLEV_110
200 # elif defined(__ADSPBF54x__) /* TBD; use default */
201 # undef CONFIG_VR_CTL_VLEV
202 # define CONFIG_VR_CTL_VLEV VLEV_120
203 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
204 # undef CONFIG_VR_CTL_VLEV
205 # define CONFIG_VR_CTL_VLEV VLEV_125
208 # ifdef CONFIG_BFIN_MAC
209 # define CONFIG_VR_CTL_CLKBUF CLKBUFOE
211 # define CONFIG_VR_CTL_CLKBUF 0
214 # if defined(__ADSPBF52x__)
215 # define CONFIG_VR_CTL_FREQ FREQ_1000
217 # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
220 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
223 /* some parts do not have an on-chip voltage regulator */
224 #if defined(__ADSPBF51x__)
225 # define CONFIG_HAS_VR 0
226 # undef CONFIG_VR_CTL_VAL
227 # define CONFIG_VR_CTL_VAL 0
229 # define CONFIG_HAS_VR 1
234 /* Blackfin with SDRAM */
235 #ifndef CONFIG_EBIU_SDBCTL_VAL
236 # if CONFIG_MEM_SIZE == 16
237 # define CONFIG_EBSZ_VAL EBSZ_16
238 # elif CONFIG_MEM_SIZE == 32
239 # define CONFIG_EBSZ_VAL EBSZ_32
240 # elif CONFIG_MEM_SIZE == 64
241 # define CONFIG_EBSZ_VAL EBSZ_64
242 # elif CONFIG_MEM_SIZE == 128
243 # define CONFIG_EBSZ_VAL EBSZ_128
244 # elif CONFIG_MEM_SIZE == 256
245 # define CONFIG_EBSZ_VAL EBSZ_256
246 # elif CONFIG_MEM_SIZE == 512
247 # define CONFIG_EBSZ_VAL EBSZ_512
249 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
251 # if CONFIG_MEM_ADD_WDTH == 8
252 # define CONFIG_EBCAW_VAL EBCAW_8
253 # elif CONFIG_MEM_ADD_WDTH == 9
254 # define CONFIG_EBCAW_VAL EBCAW_9
255 # elif CONFIG_MEM_ADD_WDTH == 10
256 # define CONFIG_EBCAW_VAL EBCAW_10
257 # elif CONFIG_MEM_ADD_WDTH == 11
258 # define CONFIG_EBCAW_VAL EBCAW_11
260 # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
262 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
267 /* Conflicting Column Address Widths Causes SDRAM Errors:
268 * EB2CAW and EB3CAW must be the same
271 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
272 # error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
276 __attribute__((always_inline)) static inline void
277 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
281 /* Save the clock pieces that are used in baud rate calculation */
282 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
284 *sdivB = bfin_read_PLL_DIV() & 0xf;
285 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
286 *divB = serial_early_get_div();
292 #ifdef CONFIG_HW_WATCHDOG
293 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
294 # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
296 /* Program the watchdog with an initial timeout of ~20 seconds.
297 * Hopefully that should be long enough to load the u-boot LDR
298 * (from wherever) and then the common u-boot code can take over.
299 * In bypass mode, the start.S would have already set a much lower
300 * timeout, so don't clobber that.
302 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
304 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
305 bfin_write_WDOG_CTL(0);
312 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
313 * fast read, so we need to slow down the SPI clock a lot more during
314 * boot. Once we switch over to u-boot's SPI flash driver, we'll
315 * increase the speed appropriately.
317 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
319 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
320 bs->dFlags |= BFLAG_FASTREAD;
321 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
328 __attribute__((always_inline)) static inline bool
329 maybe_self_refresh(ADI_BOOT_DATA *bs)
333 if (!CONFIG_MEM_SIZE)
336 /* If external memory is enabled, put it into self refresh first. */
337 #if defined(EBIU_RSTCTL)
338 if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
340 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
343 #elif defined(EBIU_SDGCTL)
344 if (bfin_read_EBIU_SDBCTL() & EBE) {
346 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
356 __attribute__((always_inline)) static inline u16
357 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
363 vr_ctl = bfin_read_VR_CTL();
367 /* If we're entering self refresh, make sure it has happened. */
369 #if defined(EBIU_RSTCTL)
370 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
372 #elif defined(EBIU_SDGCTL)
373 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
381 /* With newer bootroms, we use the helper function to set up
382 * the memory controller. Older bootroms lacks such helpers
383 * so we do it ourselves.
385 if (!ANOMALY_05000386) {
388 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
389 ADI_SYSCTRL_VALUES memory_settings;
390 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
391 if (!ANOMALY_05000440)
392 actions |= SYSCTRL_PLLDIV;
394 actions |= SYSCTRL_VRCTL;
395 if (CONFIG_VR_CTL_VAL & FREQ_MASK)
396 actions |= SYSCTRL_INTVOLTAGE;
398 actions |= SYSCTRL_EXTVOLTAGE;
399 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
401 actions |= SYSCTRL_EXTVOLTAGE;
402 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
403 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
404 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
406 bfin_write_SIC_IWR1(0);
409 bfrom_SysControl(actions, &memory_settings, NULL);
411 if (ANOMALY_05000440)
412 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
414 bfin_write_SIC_IWR1(-1);
417 bfin_write_SICA_IWR0(-1);
418 bfin_write_SICA_IWR1(-1);
424 /* Disable all peripheral wakeups except for the PLL event. */
426 bfin_write_SIC_IWR0(1);
427 bfin_write_SIC_IWR1(0);
429 bfin_write_SIC_IWR2(0);
431 #elif defined(SICA_IWR0)
432 bfin_write_SICA_IWR0(1);
433 bfin_write_SICA_IWR1(0);
435 bfin_write_SIC_IWR(1);
440 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
441 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
445 /* Only reprogram when needed to avoid triggering unnecessary
446 * PLL relock sequences.
448 if (vr_ctl != CONFIG_VR_CTL_VAL) {
450 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
457 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
461 /* Only reprogram when needed to avoid triggering unnecessary
462 * PLL relock sequences.
464 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
466 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
473 /* Restore all peripheral wakeups. */
475 bfin_write_SIC_IWR0(-1);
476 bfin_write_SIC_IWR1(-1);
478 bfin_write_SIC_IWR2(-1);
480 #elif defined(SICA_IWR0)
481 bfin_write_SICA_IWR0(-1);
482 bfin_write_SICA_IWR1(-1);
484 bfin_write_SIC_IWR(-1);
495 __attribute__((always_inline)) static inline void
496 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
500 /* Since we've changed the SCLK above, we may need to update
501 * the UART divisors (UART baud rates are based on SCLK).
502 * Do the division by hand as there are no native instructions
503 * for dividing which means we'd generate a libgcc reference.
505 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
507 unsigned int sdivR, vcoR;
508 sdivR = bfin_read_PLL_DIV() & 0xf;
509 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
510 int dividend = sdivB * divB * vcoR;
511 int divisor = vcoB * sdivR;
512 unsigned int quotient;
513 for (quotient = 0; dividend > 0; ++quotient)
515 serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230);
522 __attribute__((always_inline)) static inline void
523 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
527 if (!CONFIG_MEM_SIZE)
532 /* Program the external memory controller before we come out of
533 * self-refresh. This only works with our SDRAM controller.
536 # ifdef CONFIG_EBIU_SDRRC_VAL
537 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
539 # ifdef CONFIG_EBIU_SDBCTL_VAL
540 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
542 # ifdef CONFIG_EBIU_SDGCTL_VAL
543 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
549 /* Now that we've reprogrammed, take things out of self refresh. */
551 #if defined(EBIU_RSTCTL)
552 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
553 #elif defined(EBIU_SDGCTL)
554 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
559 /* Our DDR controller sucks and cannot be programmed while in
560 * self-refresh. So we have to pull it out before programming.
563 # ifdef CONFIG_EBIU_RSTCTL_VAL
564 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
566 # ifdef CONFIG_EBIU_DDRCTL0_VAL
567 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
569 # ifdef CONFIG_EBIU_DDRCTL1_VAL
570 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
572 # ifdef CONFIG_EBIU_DDRCTL2_VAL
573 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
575 # ifdef CONFIG_EBIU_DDRCTL3_VAL
576 /* default is disable, so don't need to force this */
577 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
579 # ifdef CONFIG_EBIU_DDRQUE_VAL
580 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
587 __attribute__((always_inline)) static inline void
588 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
592 if (!CONFIG_MEM_SIZE)
597 /* Are we coming out of hibernate (suspend to memory) ?
598 * The memory layout is:
599 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
600 * 0x4: return address
603 * SCKELOW is unreliable on older parts (anomaly 307)
605 if (ANOMALY_05000307 || vr_ctl & 0x8000) {
606 uint32_t *hibernate_magic = 0;
607 __builtin_bfin_ssync(); /* make sure memory controller is done */
608 if (hibernate_magic[0] == 0xDEADBEEF) {
610 bfin_write_EVT15(hibernate_magic[1]);
611 bfin_write_IMASK(EVT_IVG15);
612 __asm__ __volatile__ (
613 /* load reti early to avoid anomaly 281 */
615 /* clear hibernate magic */
617 /* load stack pointer */
619 /* lower ourselves from reset ivg to ivg15 */
623 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
632 BOOTROM_CALLED_FUNC_ATTR
633 void initcode(ADI_BOOT_DATA *bs)
635 ADI_BOOT_DATA bootstruct_scratch;
637 /* Setup NMI handler before anything else */
638 program_nmi_handler();
644 /* If the bootstruct is NULL, then it's because we're loading
645 * dynamically and not via LDR (bootrom). So set the struct to
646 * some scratch space.
649 bs = &bootstruct_scratch;
652 bool put_into_srfs = maybe_self_refresh(bs);
655 uint sdivB, divB, vcoB;
656 program_early_devices(bs, &sdivB, &divB, &vcoB);
659 u16 vr_ctl = program_clocks(bs, put_into_srfs);
662 update_serial_clocks(bs, sdivB, divB, vcoB);
665 program_memory_controller(bs, put_into_srfs);
668 check_hibernation(bs, vr_ctl, put_into_srfs);
671 program_async_controller(bs);
673 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
675 /* Tell the bootrom where our entry point is so that it knows
676 * where to jump to when finishing processing the LDR. This
677 * allows us to avoid small jump blocks in the LDR, and also
678 * works around anomaly 05000389 (init address in external
679 * memory causes bootrom to trigger external addressing IVHW).
681 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
682 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);