arch/blackfin/cpu/initcode.c

   1 /*
   2  * initcode.c - Initialize the processor.  This is usually entails things
   3  * like external memory, voltage regulators, etc...  Note that this file
   4  * cannot make any function calls as it may be executed all by itself by
   5  * the Blackfin's bootrom in LDR format.
   6  *
   7  * Copyright (c) 2004-2011 Analog Devices Inc.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #define BFIN_IN_INITCODE
  13
  14 #include <config.h>
  15 #include <asm/blackfin.h>
  16 #include <asm/mach-common/bits/bootrom.h>
  17 #include <asm/mach-common/bits/core.h>
  18
  19 #define BUG() while (1) { asm volatile("emuexcpt;"); }
  20
  21 #include "serial.h"
  22
  23 #ifndef __ADSPBF60x__
  24 #include <asm/mach-common/bits/ebiu.h>
  25 #include <asm/mach-common/bits/pll.h>
  26 #else /* __ADSPBF60x__ */
  27 #include <asm/mach-common/bits/cgu.h>
  28
  29 #define CONFIG_BFIN_GET_DCLK_M \
  30         ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
  31
  32 #ifndef CONFIG_DMC_DDRCFG
  33 #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
  34         (CONFIG_BFIN_GET_DCLK_M != 133) && \
  35         (CONFIG_BFIN_GET_DCLK_M != 150) && \
  36         (CONFIG_BFIN_GET_DCLK_M != 166) && \
  37         (CONFIG_BFIN_GET_DCLK_M != 200) && \
  38         (CONFIG_BFIN_GET_DCLK_M != 225) && \
  39         (CONFIG_BFIN_GET_DCLK_M != 250))
  40 #error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
  41 #endif
  42 #endif
  43
  44 /* DMC control bits */
  45 #define SRREQ                   0x8
  46
  47 /* DMC status bits */
  48 #define IDLE                    0x1
  49 #define MEMINITDONE             0x4
  50 #define SRACK                   0x8
  51 #define PDACK                   0x10
  52 #define DPDACK                  0x20
  53 #define DLLCALDONE              0x2000
  54 #define PENDREF                 0xF0000
  55 #define PHYRDPHASE              0xF00000
  56 #define PHYRDPHASE_OFFSET       20
  57
  58 /* DMC DLL control bits */
  59 #define DLLCALRDCNT             0xFF
  60 #define DATACYC_OFFSET          8
  61
  62 struct ddr_config {
  63         u32 ddr_clk;
  64         u32 dmc_ddrctl;
  65         u32 dmc_ddrcfg;
  66         u32 dmc_ddrtr0;
  67         u32 dmc_ddrtr1;
  68         u32 dmc_ddrtr2;
  69         u32 dmc_ddrmr;
  70         u32 dmc_ddrmr1;
  71 };
  72
  73 static struct ddr_config ddr_config_table[] = {
  74         [0] = {
  75                 .ddr_clk    = 125,      /* 125MHz */
  76                 .dmc_ddrctl = 0x00000904,
  77                 .dmc_ddrcfg = 0x00000422,
  78                 .dmc_ddrtr0 = 0x20705212,
  79                 .dmc_ddrtr1 = 0x201003CF,
  80                 .dmc_ddrtr2 = 0x00320107,
  81                 .dmc_ddrmr  = 0x00000422,
  82                 .dmc_ddrmr1 = 0x4,
  83         },
  84         [1] = {
  85                 .ddr_clk    = 133,      /* 133MHz */
  86                 .dmc_ddrctl = 0x00000904,
  87                 .dmc_ddrcfg = 0x00000422,
  88                 .dmc_ddrtr0 = 0x20806313,
  89                 .dmc_ddrtr1 = 0x2013040D,
  90                 .dmc_ddrtr2 = 0x00320108,
  91                 .dmc_ddrmr  = 0x00000632,
  92                 .dmc_ddrmr1 = 0x4,
  93         },
  94         [2] = {
  95                 .ddr_clk    = 150,      /* 150MHz */
  96                 .dmc_ddrctl = 0x00000904,
  97                 .dmc_ddrcfg = 0x00000422,
  98                 .dmc_ddrtr0 = 0x20A07323,
  99                 .dmc_ddrtr1 = 0x20160492,
 100                 .dmc_ddrtr2 = 0x00320209,
 101                 .dmc_ddrmr  = 0x00000632,
 102                 .dmc_ddrmr1 = 0x4,
 103         },
 104         [3] = {
 105                 .ddr_clk    = 166,      /* 166MHz */
 106                 .dmc_ddrctl = 0x00000904,
 107                 .dmc_ddrcfg = 0x00000422,
 108                 .dmc_ddrtr0 = 0x20A07323,
 109                 .dmc_ddrtr1 = 0x2016050E,
 110                 .dmc_ddrtr2 = 0x00320209,
 111                 .dmc_ddrmr  = 0x00000632,
 112                 .dmc_ddrmr1 = 0x4,
 113         },
 114         [4] = {
 115                 .ddr_clk    = 200,      /* 200MHz */
 116                 .dmc_ddrctl = 0x00000904,
 117                 .dmc_ddrcfg = 0x00000422,
 118                 .dmc_ddrtr0 = 0x20a07323,
 119                 .dmc_ddrtr1 = 0x2016050f,
 120                 .dmc_ddrtr2 = 0x00320509,
 121                 .dmc_ddrmr  = 0x00000632,
 122                 .dmc_ddrmr1 = 0x4,
 123         },
 124         [5] = {
 125                 .ddr_clk    = 225,      /* 225MHz */
 126                 .dmc_ddrctl = 0x00000904,
 127                 .dmc_ddrcfg = 0x00000422,
 128                 .dmc_ddrtr0 = 0x20E0A424,
 129                 .dmc_ddrtr1 = 0x302006DB,
 130                 .dmc_ddrtr2 = 0x0032020D,
 131                 .dmc_ddrmr  = 0x00000842,
 132                 .dmc_ddrmr1 = 0x4,
 133         },
 134         [6] = {
 135                 .ddr_clk    = 250,      /* 250MHz */
 136                 .dmc_ddrctl = 0x00000904,
 137                 .dmc_ddrcfg = 0x00000422,
 138                 .dmc_ddrtr0 = 0x20E0A424,
 139                 .dmc_ddrtr1 = 0x3020079E,
 140                 .dmc_ddrtr2 = 0x0032050D,
 141                 .dmc_ddrmr  = 0x00000842,
 142                 .dmc_ddrmr1 = 0x4,
 143         },
 144 };
 145 #endif /* __ADSPBF60x__ */
 146
 147 __attribute__((always_inline))
 148 static inline void serial_init(void)
 149 {
 150         uint32_t uart_base = UART_BASE;
 151
 152 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 153 # ifdef BFIN_BOOT_UART_USE_RTS
 154 #  define BFIN_UART_USE_RTS 1
 155 # else
 156 #  define BFIN_UART_USE_RTS 0
 157 # endif
 158         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 159                 size_t i;
 160
 161                 /* force RTS rather than relying on auto RTS */
 162 #if BFIN_UART_HW_VER < 4
 163                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
 164 #else
 165                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
 166                                 FCPOL);
 167 #endif
 168
 169                 /* Wait for the line to clear up.  We cannot rely on UART
 170                  * registers as none of them reflect the status of the RSR.
 171                  * Instead, we'll sleep for ~10 bit times at 9600 baud.
 172                  * We can precalc things here by assuming boot values for
 173                  * PLL rather than loading registers and calculating.
 174                  *      baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
 175                  *      EDB0    = 0
 176                  *      Divisor = (SCLK / baud) / 16
 177                  *      SCLK    = baud * 16 * Divisor
 178                  *      SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
 179                  *      CCLK    = (16 * Divisor * 5) * (9600 / 10)
 180                  * In reality, this will probably be just about 1 second delay,
 181                  * so assuming 9600 baud is OK (both as a very low and too high
 182                  * speed as this will buffer things enough).
 183                  */
 184 #define _NUMBITS (10)                                   /* how many bits to delay */
 185 #define _LOWBAUD (9600)                                 /* low baud rate */
 186 #define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
 187 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
 188 #define _NUMINS  (3)                                    /* how many instructions in loop */
 189 #define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
 190                 i = _CCLK;
 191                 while (i--)
 192                         asm volatile("" : : : "memory");
 193         }
 194 #endif
 195
 196         if (BFIN_DEBUG_EARLY_SERIAL) {
 197                 int enabled = serial_early_enabled(uart_base);
 198
 199                 serial_early_init(uart_base);
 200
 201                 /* If the UART is off, that means we need to program
 202                  * the baud rate ourselves initially.
 203                  */
 204                 if (!enabled)
 205                         serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
 206         }
 207 }
 208
 209 __attribute__((always_inline))
 210 static inline void serial_deinit(void)
 211 {
 212 #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 213         uint32_t uart_base = UART_BASE;
 214
 215         if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 216                 /* clear forced RTS rather than relying on auto RTS */
 217 #if BFIN_UART_HW_VER < 4
 218                 bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
 219 #else
 220                 bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
 221                                 ~FCPOL);
 222 #endif
 223         }
 224 #endif
 225 }
 226
 227 __attribute__((always_inline))
 228 static inline void serial_putc(char c)
 229 {
 230         uint32_t uart_base = UART_BASE;
 231
 232         if (!BFIN_DEBUG_EARLY_SERIAL)
 233                 return;
 234
 235         if (c == '\n')
 236                 serial_putc('\r');
 237
 238         bfin_write(&pUART->thr, c);
 239
 240         while (!(_lsr_read(pUART) & TEMT))
 241                 continue;
 242 }
 243
 244 #include "initcode.h"
 245
 246 __attribute__((always_inline)) static inline void
 247 program_nmi_handler(void)
 248 {
 249         u32 tmp1, tmp2;
 250
 251         /* Older bootroms don't create a dummy NMI handler,
 252          * so make one ourselves ASAP in case it fires.
 253          */
 254         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
 255                 return;
 256
 257         asm volatile (
 258                 "%0 = RETS;" /* Save current RETS */
 259                 "CALL 1f;"   /* Figure out current PC */
 260                 "RTN;"       /* The simple NMI handler */
 261                 "1:"
 262                 "%1 = RETS;" /* Load addr of NMI handler */
 263                 "RETS = %0;" /* Restore RETS */
 264                 "[%2] = %1;" /* Write NMI handler */
 265                 : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
 266         );
 267 }
 268
 269 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
 270  * us a freq of 16MHz for SPI which should generally be
 271  * slow enough for the slow reads the bootrom uses.
 272  */
 273 #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
 274     ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
 275      (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
 276 # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
 277 #else
 278 # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
 279 #endif
 280 #ifndef CONFIG_SPI_BAUD_INITBLOCK
 281 # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
 282 #endif
 283 #ifdef SPI0_BAUD
 284 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
 285 #endif
 286
 287 #ifdef __ADSPBF60x__
 288
 289 #ifndef CONFIG_CGU_CTL_VAL
 290 # define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
 291 #endif
 292
 293 #ifndef CONFIG_CGU_DIV_VAL
 294 # define CONFIG_CGU_DIV_VAL \
 295         ((CONFIG_CCLK_DIV   << CSEL_P)   | \
 296          (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
 297          (CONFIG_SCLK_DIV << SYSSEL_P) | \
 298          (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
 299          (CONFIG_DCLK_DIV   << DSEL_P)   | \
 300          (CONFIG_OCLK_DIV   << OSEL_P))
 301 #endif
 302
 303 #else /* __ADSPBF60x__ */
 304
 305 /* PLL_DIV defines */
 306 #ifndef CONFIG_PLL_DIV_VAL
 307 # if (CONFIG_CCLK_DIV == 1)
 308 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
 309 # elif (CONFIG_CCLK_DIV == 2)
 310 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
 311 # elif (CONFIG_CCLK_DIV == 4)
 312 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
 313 # elif (CONFIG_CCLK_DIV == 8)
 314 #  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
 315 # else
 316 #  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
 317 # endif
 318 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
 319 #endif
 320
 321 #ifndef CONFIG_PLL_LOCKCNT_VAL
 322 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
 323 #endif
 324
 325 #ifndef CONFIG_PLL_CTL_VAL
 326 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
 327 #endif
 328
 329 /* Make sure our voltage value is sane so we don't blow up! */
 330 #ifndef CONFIG_VR_CTL_VAL
 331 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
 332 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
 333 #  define CCLK_VLEV_120 400000000
 334 #  define CCLK_VLEV_125 533000000
 335 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
 336 #  define CCLK_VLEV_120 401000000
 337 #  define CCLK_VLEV_125 401000000
 338 # elif defined(__ADSPBF561__)
 339 #  define CCLK_VLEV_120 300000000
 340 #  define CCLK_VLEV_125 501000000
 341 # endif
 342 # if BFIN_CCLK < CCLK_VLEV_120
 343 #  define CONFIG_VR_CTL_VLEV VLEV_120
 344 # elif BFIN_CCLK < CCLK_VLEV_125
 345 #  define CONFIG_VR_CTL_VLEV VLEV_125
 346 # else
 347 #  define CONFIG_VR_CTL_VLEV VLEV_130
 348 # endif
 349 # if defined(__ADSPBF52x__)     /* TBD; use default */
 350 #  undef CONFIG_VR_CTL_VLEV
 351 #  define CONFIG_VR_CTL_VLEV VLEV_110
 352 # elif defined(__ADSPBF54x__)   /* TBD; use default */
 353 #  undef CONFIG_VR_CTL_VLEV
 354 #  define CONFIG_VR_CTL_VLEV VLEV_120
 355 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
 356 #  undef CONFIG_VR_CTL_VLEV
 357 #  define CONFIG_VR_CTL_VLEV VLEV_125
 358 # endif
 359
 360 # ifdef CONFIG_BFIN_MAC
 361 #  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
 362 # else
 363 #  define CONFIG_VR_CTL_CLKBUF 0
 364 # endif
 365
 366 # if defined(__ADSPBF52x__)
 367 #  define CONFIG_VR_CTL_FREQ FREQ_1000
 368 # else
 369 #  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
 370 # endif
 371
 372 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
 373 #endif
 374
 375 /* some parts do not have an on-chip voltage regulator */
 376 #if defined(__ADSPBF51x__)
 377 # define CONFIG_HAS_VR 0
 378 # undef CONFIG_VR_CTL_VAL
 379 # define CONFIG_VR_CTL_VAL 0
 380 #else
 381 # define CONFIG_HAS_VR 1
 382 #endif
 383
 384 #if CONFIG_MEM_SIZE
 385 #ifndef EBIU_RSTCTL
 386 /* Blackfin with SDRAM */
 387 #ifndef CONFIG_EBIU_SDBCTL_VAL
 388 # if CONFIG_MEM_SIZE == 16
 389 #  define CONFIG_EBSZ_VAL EBSZ_16
 390 # elif CONFIG_MEM_SIZE == 32
 391 #  define CONFIG_EBSZ_VAL EBSZ_32
 392 # elif CONFIG_MEM_SIZE == 64
 393 #  define CONFIG_EBSZ_VAL EBSZ_64
 394 # elif CONFIG_MEM_SIZE == 128
 395 #  define CONFIG_EBSZ_VAL EBSZ_128
 396 # elif CONFIG_MEM_SIZE == 256
 397 #  define CONFIG_EBSZ_VAL EBSZ_256
 398 # elif CONFIG_MEM_SIZE == 512
 399 #  define CONFIG_EBSZ_VAL EBSZ_512
 400 # else
 401 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
 402 # endif
 403 # if CONFIG_MEM_ADD_WDTH == 8
 404 #  define CONFIG_EBCAW_VAL EBCAW_8
 405 # elif CONFIG_MEM_ADD_WDTH == 9
 406 #  define CONFIG_EBCAW_VAL EBCAW_9
 407 # elif CONFIG_MEM_ADD_WDTH == 10
 408 #  define CONFIG_EBCAW_VAL EBCAW_10
 409 # elif CONFIG_MEM_ADD_WDTH == 11
 410 #  define CONFIG_EBCAW_VAL EBCAW_11
 411 # else
 412 #  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
 413 # endif
 414 # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
 415 #endif
 416 #endif
 417 #endif
 418
 419 /* Conflicting Column Address Widths Causes SDRAM Errors:
 420  * EB2CAW and EB3CAW must be the same
 421  */
 422 #if ANOMALY_05000362
 423 # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
 424 #  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
 425 # endif
 426 #endif
 427
 428 #endif /*  __ADSPBF60x__ */
 429
 430 __attribute__((always_inline)) static inline void
 431 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 432 {
 433         serial_putc('a');
 434
 435         /* Save the clock pieces that are used in baud rate calculation */
 436         if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 437                 serial_putc('b');
 438 #ifdef __ADSPBF60x__
 439                 *sdivB = bfin_read_CGU_DIV();
 440                 *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
 441                 *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 442 #else
 443                 *sdivB = bfin_read_PLL_DIV() & 0xf;
 444                 *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 445 #endif
 446                 *divB = serial_early_get_div();
 447                 serial_putc('c');
 448         }
 449
 450         serial_putc('d');
 451
 452 #ifdef CONFIG_HW_WATCHDOG
 453 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
 454 #  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
 455 # endif
 456         /* Program the watchdog with an initial timeout of ~20 seconds.
 457          * Hopefully that should be long enough to load the u-boot LDR
 458          * (from wherever) and then the common u-boot code can take over.
 459          * In bypass mode, the start.S would have already set a much lower
 460          * timeout, so don't clobber that.
 461          */
 462         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
 463                 serial_putc('e');
 464                 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
 465                 bfin_write_WDOG_CTL(0);
 466                 serial_putc('f');
 467         }
 468 #endif
 469
 470         serial_putc('g');
 471
 472         /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
 473          * fast read, so we need to slow down the SPI clock a lot more during
 474          * boot.  Once we switch over to u-boot's SPI flash driver, we'll
 475          * increase the speed appropriately.
 476          */
 477 #ifdef SPI_BAUD
 478         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
 479                 serial_putc('h');
 480                 if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
 481                         bs->dFlags |= BFLAG_FASTREAD;
 482                 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
 483                 serial_putc('i');
 484         }
 485 #endif
 486
 487         serial_putc('j');
 488 }
 489
 490 __attribute__((always_inline)) static inline bool
 491 maybe_self_refresh(ADI_BOOT_DATA *bs)
 492 {
 493         serial_putc('a');
 494
 495         if (!CONFIG_MEM_SIZE)
 496                 return false;
 497
 498 #ifdef __ADSPBF60x__
 499
 500 #else /* __ADSPBF60x__ */
 501
 502         /* If external memory is enabled, put it into self refresh first. */
 503 #if defined(EBIU_RSTCTL)
 504         if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
 505                 serial_putc('b');
 506                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
 507                 return true;
 508         }
 509 #elif defined(EBIU_SDGCTL)
 510         if (bfin_read_EBIU_SDBCTL() & EBE) {
 511                 serial_putc('b');
 512                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
 513                 return true;
 514         }
 515 #endif
 516
 517 #endif /* __ADSPBF60x__ */
 518         serial_putc('c');
 519
 520         return false;
 521 }
 522
 523 __attribute__((always_inline)) static inline u16
 524 program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 525 {
 526         u16 vr_ctl;
 527
 528         serial_putc('a');
 529
 530 #ifdef __ADSPBF60x__
 531         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 532                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
 533                 SSYNC();
 534                 while (!(bfin_read_DMC0_STAT() & SRACK))
 535                         continue;
 536         }
 537
 538         /* Don't set the same value of MSEL and DF to CGU_CTL */
 539         if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
 540                         != CONFIG_CGU_CTL_VAL) {
 541                 bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
 542                 bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
 543                 while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
 544                                 !(bfin_read_CGU_STAT() & PLLLK))
 545                         continue;
 546         }
 547
 548         bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
 549         while (bfin_read_CGU_STAT() & CLKSALGN)
 550                 continue;
 551
 552         if (bfin_read_DMC0_STAT() & MEMINITDONE) {
 553                 bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
 554                 SSYNC();
 555                 while (bfin_read_DMC0_STAT() & SRACK)
 556                         continue;
 557         }
 558
 559 #else /* __ADSPBF60x__ */
 560
 561         vr_ctl = bfin_read_VR_CTL();
 562
 563         serial_putc('b');
 564
 565         /* If we're entering self refresh, make sure it has happened. */
 566         if (put_into_srfs)
 567 #if defined(EBIU_RSTCTL)
 568                 while (!(bfin_read_EBIU_RSTCTL() & SRACK))
 569                         continue;
 570 #elif defined(EBIU_SDGCTL)
 571                 while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
 572                         continue;
 573 #else
 574                 ;
 575 #endif
 576
 577         serial_putc('c');
 578
 579         /* With newer bootroms, we use the helper function to set up
 580          * the memory controller.  Older bootroms lacks such helpers
 581          * so we do it ourselves.
 582          */
 583         if (!ANOMALY_05000386) {
 584                 serial_putc('d');
 585
 586                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 587                 ADI_SYSCTRL_VALUES memory_settings;
 588                 uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
 589                 if (!ANOMALY_05000440)
 590                         actions |= SYSCTRL_PLLDIV;
 591                 if (CONFIG_HAS_VR) {
 592                         actions |= SYSCTRL_VRCTL;
 593                         if (CONFIG_VR_CTL_VAL & FREQ_MASK)
 594                                 actions |= SYSCTRL_INTVOLTAGE;
 595                         else
 596                                 actions |= SYSCTRL_EXTVOLTAGE;
 597                         memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
 598                 } else
 599                         actions |= SYSCTRL_EXTVOLTAGE;
 600                 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
 601                 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
 602                 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
 603 #if ANOMALY_05000432
 604                 bfin_write_SIC_IWR1(0);
 605 #endif
 606                 serial_putc('e');
 607                 bfrom_SysControl(actions, &memory_settings, NULL);
 608                 serial_putc('f');
 609                 if (ANOMALY_05000440)
 610                         bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 611 #if ANOMALY_05000432
 612                 bfin_write_SIC_IWR1(-1);
 613 #endif
 614 #if ANOMALY_05000171
 615                 bfin_write_SICA_IWR0(-1);
 616                 bfin_write_SICA_IWR1(-1);
 617 #endif
 618                 serial_putc('g');
 619         } else {
 620                 serial_putc('h');
 621
 622                 /* Disable all peripheral wakeups except for the PLL event. */
 623 #ifdef SIC_IWR0
 624                 bfin_write_SIC_IWR0(1);
 625                 bfin_write_SIC_IWR1(0);
 626 # ifdef SIC_IWR2
 627                 bfin_write_SIC_IWR2(0);
 628 # endif
 629 #elif defined(SICA_IWR0)
 630                 bfin_write_SICA_IWR0(1);
 631                 bfin_write_SICA_IWR1(0);
 632 #elif defined(SIC_IWR)
 633                 bfin_write_SIC_IWR(1);
 634 #endif
 635
 636                 serial_putc('i');
 637
 638                 /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 639                 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
 640
 641                 serial_putc('j');
 642
 643                 /* Only reprogram when needed to avoid triggering unnecessary
 644                  * PLL relock sequences.
 645                  */
 646                 if (vr_ctl != CONFIG_VR_CTL_VAL) {
 647                         serial_putc('?');
 648                         bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
 649                         asm("idle;");
 650                         serial_putc('!');
 651                 }
 652
 653                 serial_putc('k');
 654
 655                 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
 656
 657                 serial_putc('l');
 658
 659                 /* Only reprogram when needed to avoid triggering unnecessary
 660                  * PLL relock sequences.
 661                  */
 662                 if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
 663                         serial_putc('?');
 664                         bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
 665                         asm("idle;");
 666                         serial_putc('!');
 667                 }
 668
 669                 serial_putc('m');
 670
 671                 /* Restore all peripheral wakeups. */
 672 #ifdef SIC_IWR0
 673                 bfin_write_SIC_IWR0(-1);
 674                 bfin_write_SIC_IWR1(-1);
 675 # ifdef SIC_IWR2
 676                 bfin_write_SIC_IWR2(-1);
 677 # endif
 678 #elif defined(SICA_IWR0)
 679                 bfin_write_SICA_IWR0(-1);
 680                 bfin_write_SICA_IWR1(-1);
 681 #elif defined(SIC_IWR)
 682                 bfin_write_SIC_IWR(-1);
 683 #endif
 684
 685                 serial_putc('n');
 686         }
 687
 688 #endif /* __ADSPBF60x__ */
 689
 690         serial_putc('o');
 691
 692         return vr_ctl;
 693 }
 694
 695 __attribute__((always_inline)) static inline void
 696 update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 697 {
 698         serial_putc('a');
 699
 700         /* Since we've changed the SCLK above, we may need to update
 701          * the UART divisors (UART baud rates are based on SCLK).
 702          * Do the division by hand as there are no native instructions
 703          * for dividing which means we'd generate a libgcc reference.
 704          */
 705         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 706                 unsigned int sdivR, vcoR;
 707                 int dividend = sdivB * divB * vcoR;
 708                 int divisor = vcoB * sdivR;
 709                 unsigned int quotient;
 710
 711                 serial_putc('b');
 712
 713 #ifdef __ADSPBF60x__
 714                 sdivR = bfin_read_CGU_DIV();
 715                 sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
 716                 vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
 717 #else
 718                 sdivR = bfin_read_PLL_DIV() & 0xf;
 719                 vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
 720 #endif
 721
 722                 for (quotient = 0; dividend > 0; ++quotient)
 723                         dividend -= divisor;
 724                 serial_early_put_div(quotient - ANOMALY_05000230);
 725                 serial_putc('c');
 726         }
 727
 728         serial_putc('d');
 729 }
 730
 731 __attribute__((always_inline)) static inline void
 732 program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 733 {
 734         serial_putc('a');
 735
 736         if (!CONFIG_MEM_SIZE)
 737                 return;
 738
 739         serial_putc('b');
 740
 741 #ifdef __ADSPBF60x__
 742         int dlldatacycle;
 743         int dll_ctl;
 744         int i = 0;
 745
 746         if (CONFIG_BFIN_GET_DCLK_M ==  125)
 747                 i = 0;
 748         else if (CONFIG_BFIN_GET_DCLK_M ==  133)
 749                 i = 1;
 750         else if (CONFIG_BFIN_GET_DCLK_M ==  150)
 751                 i = 2;
 752         else if (CONFIG_BFIN_GET_DCLK_M ==  166)
 753                 i = 3;
 754         else if (CONFIG_BFIN_GET_DCLK_M ==  200)
 755                 i = 4;
 756         else if (CONFIG_BFIN_GET_DCLK_M ==  225)
 757                 i = 5;
 758         else if (CONFIG_BFIN_GET_DCLK_M ==  250)
 759                 i = 6;
 760
 761 #if 0
 762         for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
 763                 if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
 764                         break;
 765 #endif
 766
 767 #ifndef CONFIG_DMC_DDRCFG
 768         bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
 769 #else
 770         bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
 771 #endif
 772 #ifndef CONFIG_DMC_DDRTR0
 773         bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
 774 #else
 775         bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
 776 #endif
 777 #ifndef CONFIG_DMC_DDRTR1
 778         bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
 779 #else
 780         bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
 781 #endif
 782 #ifndef CONFIG_DMC_DDRTR2
 783         bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
 784 #else
 785         bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
 786 #endif
 787 #ifndef CONFIG_DMC_DDRMR
 788         bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
 789 #else
 790         bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
 791 #endif
 792 #ifndef CONFIG_DMC_DDREMR1
 793         bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
 794 #else
 795         bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
 796 #endif
 797 #ifndef CONFIG_DMC_DDRCTL
 798         bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
 799 #else
 800         bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
 801 #endif
 802
 803         SSYNC();
 804         while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
 805                 continue;
 806
 807         dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
 808                         PHYRDPHASE_OFFSET;
 809         dll_ctl = bfin_read_DMC0_DLLCTL();
 810         dll_ctl &= 0x0ff;
 811         bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
 812
 813         SSYNC();
 814         while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
 815                 continue;
 816         serial_putc('!');
 817 #else /* __ADSPBF60x__ */
 818
 819         /* Program the external memory controller before we come out of
 820          * self-refresh.  This only works with our SDRAM controller.
 821          */
 822 #ifdef EBIU_SDGCTL
 823 # ifdef CONFIG_EBIU_SDRRC_VAL
 824         bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
 825 # endif
 826 # ifdef CONFIG_EBIU_SDBCTL_VAL
 827         bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
 828 # endif
 829 # ifdef CONFIG_EBIU_SDGCTL_VAL
 830         bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
 831 # endif
 832 #endif
 833
 834         serial_putc('c');
 835
 836         /* Now that we've reprogrammed, take things out of self refresh. */
 837         if (put_into_srfs)
 838 #if defined(EBIU_RSTCTL)
 839                 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
 840 #elif defined(EBIU_SDGCTL)
 841                 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
 842 #endif
 843
 844         serial_putc('d');
 845
 846         /* Our DDR controller sucks and cannot be programmed while in
 847          * self-refresh.  So we have to pull it out before programming.
 848          */
 849 #ifdef EBIU_RSTCTL
 850 # ifdef CONFIG_EBIU_RSTCTL_VAL
 851         bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
 852 # endif
 853 # ifdef CONFIG_EBIU_DDRCTL0_VAL
 854         bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
 855 # endif
 856 # ifdef CONFIG_EBIU_DDRCTL1_VAL
 857         bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
 858 # endif
 859 # ifdef CONFIG_EBIU_DDRCTL2_VAL
 860         bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
 861 # endif
 862 # ifdef CONFIG_EBIU_DDRCTL3_VAL
 863         /* default is disable, so don't need to force this */
 864         bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
 865 # endif
 866 # ifdef CONFIG_EBIU_DDRQUE_VAL
 867         bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
 868 # endif
 869 #endif
 870
 871 #endif /* __ADSPBF60x__ */
 872         serial_putc('e');
 873 }
 874
 875 __attribute__((always_inline)) static inline void
 876 check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
 877 {
 878         serial_putc('a');
 879
 880         if (!CONFIG_MEM_SIZE)
 881                 return;
 882
 883         serial_putc('b');
 884
 885         /* Are we coming out of hibernate (suspend to memory) ?
 886          * The memory layout is:
 887          * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
 888          * 0x4: return address
 889          * 0x8: stack pointer
 890          *
 891          * SCKELOW is unreliable on older parts (anomaly 307)
 892          */
 893         if (ANOMALY_05000307 || vr_ctl & 0x8000) {
 894                 uint32_t *hibernate_magic = 0;
 895
 896                 SSYNC();
 897                 if (hibernate_magic[0] == 0xDEADBEEF) {
 898                         serial_putc('c');
 899                         bfin_write_EVT15(hibernate_magic[1]);
 900                         bfin_write_IMASK(EVT_IVG15);
 901                         __asm__ __volatile__ (
 902                                 /* load reti early to avoid anomaly 281 */
 903                                 "reti = %0;"
 904                                 /* clear hibernate magic */
 905                                 "[%0] = %1;"
 906                                 /* load stack pointer */
 907                                 "SP = [%0 + 8];"
 908                                 /* lower ourselves from reset ivg to ivg15 */
 909                                 "raise 15;"
 910                                 "rti;"
 911                                 :
 912                                 : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
 913                         );
 914                 }
 915                 serial_putc('d');
 916         }
 917
 918         serial_putc('e');
 919 }
 920
 921 BOOTROM_CALLED_FUNC_ATTR
 922 void initcode(ADI_BOOT_DATA *bs)
 923 {
 924         ADI_BOOT_DATA bootstruct_scratch;
 925
 926         /* Setup NMI handler before anything else */
 927         program_nmi_handler();
 928
 929         serial_init();
 930
 931         serial_putc('A');
 932
 933         /* If the bootstruct is NULL, then it's because we're loading
 934          * dynamically and not via LDR (bootrom).  So set the struct to
 935          * some scratch space.
 936          */
 937         if (!bs)
 938                 bs = &bootstruct_scratch;
 939
 940         serial_putc('B');
 941         bool put_into_srfs = maybe_self_refresh(bs);
 942
 943         serial_putc('C');
 944         uint sdivB, divB, vcoB;
 945         program_early_devices(bs, &sdivB, &divB, &vcoB);
 946
 947         serial_putc('D');
 948         u16 vr_ctl = program_clocks(bs, put_into_srfs);
 949
 950         serial_putc('E');
 951         update_serial_clocks(bs, sdivB, divB, vcoB);
 952
 953         serial_putc('F');
 954         program_memory_controller(bs, put_into_srfs);
 955
 956         serial_putc('G');
 957         check_hibernation(bs, vr_ctl, put_into_srfs);
 958
 959         serial_putc('H');
 960         program_async_controller(bs);
 961
 962 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
 963         serial_putc('I');
 964         /* Tell the bootrom where our entry point is so that it knows
 965          * where to jump to when finishing processing the LDR.  This
 966          * allows us to avoid small jump blocks in the LDR, and also
 967          * works around anomaly 05000389 (init address in external
 968          * memory causes bootrom to trigger external addressing IVHW).
 969          */
 970         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
 971                 bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
 972 #endif
 973
 974         serial_putc('>');
 975         serial_putc('\n');
 976
 977         serial_deinit();
 978 }