2 * Based on arch/arm/mm/proc.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
23 #include <asm/assembler.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/cpufeature.h>
29 #include <asm/alternative.h>
31 #ifdef CONFIG_ARM64_64K_PAGES
32 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
33 #elif defined(CONFIG_ARM64_16K_PAGES)
34 #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
35 #else /* CONFIG_ARM64_4K_PAGES */
36 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
39 #define TCR_SMP_FLAGS TCR_SHARED
41 /* PTWs cacheable, inner/outer WBWA */
42 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
44 #define MAIR(attr, mt) ((attr) << ((mt) * 8))
49 * Idle the processor (wait for interrupt).
52 dsb sy // WFI may enter a low-power mode
59 * cpu_do_suspend - save CPU registers context
61 * x0: virtual address of context pointer
66 mrs x4, contextidr_el1
78 stp x10, x11, [x0, #64]
80 ENDPROC(cpu_do_suspend)
83 * cpu_do_resume - restore CPU register context
85 * x0: Address of context pointer
87 .pushsection ".idmap.text", "awx"
92 ldp x9, x10, [x0, #48]
93 ldp x11, x12, [x0, #64]
96 msr contextidr_el1, x4
99 /* Don't change t0sz here, mask those bits when restoring */
101 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
107 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
108 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
109 * exception. Mask them until local_dbg_restore() in cpu_suspend()
117 * Restore oslsr_el1 by writing oslar_el1
120 ubfx x11, x11, #1, #1
122 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
125 ENDPROC(cpu_do_resume)
130 * cpu_do_switch_mm(pgd_phys, tsk)
132 * Set the translation table base pointer to be pgd_phys.
134 * - pgd_phys - physical address of new TTB
136 ENTRY(cpu_do_switch_mm)
138 mmid x1, x1 // get mm->context.id
139 bfi x2, x1, #48, #16 // set the ASID
140 msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
142 msr ttbr0_el1, x0 // now update TTBR0
144 b post_ttbr_update_workaround // Back to C code...
145 ENDPROC(cpu_do_switch_mm)
147 .pushsection ".idmap.text", "awx"
149 .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
150 adrp \tmp1, empty_zero_page
159 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
161 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
162 * called by anything else. It can only be executed from a TTBR0 mapping.
164 ENTRY(idmap_cpu_replace_ttbr1)
168 __idmap_cpu_set_reserved_ttbr1 x1, x3
176 ENDPROC(idmap_cpu_replace_ttbr1)
179 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
180 .pushsection ".idmap.text", "awx"
182 .macro __idmap_kpti_get_pgtable_ent, type
183 dc cvac, cur_\()\type\()p // Ensure any existing dirty
184 dmb sy // lines are written back before
185 ldr \type, [cur_\()\type\()p] // loading the entry
186 tbz \type, #0, skip_\()\type // Skip invalid and
187 tbnz \type, #11, skip_\()\type // non-global entries
190 .macro __idmap_kpti_put_pgtable_ent_ng, type
191 orr \type, \type, #PTE_NG // Same bit for blocks and pages
192 str \type, [cur_\()\type\()p] // Update the entry and ensure
193 dmb sy // that it is visible to all
194 dc civac, cur_\()\type\()p // CPUs.
198 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
200 * Called exactly once from stop_machine context by each CPU found during boot.
204 ENTRY(idmap_kpti_install_ng_mappings)
223 mrs swapper_ttb, ttbr1_el1
224 adr flag_ptr, __idmap_kpti_flag
226 cbnz cpu, __idmap_kpti_secondary
228 /* We're the boot CPU. Wait for the others to catch up */
231 ldaxr w18, [flag_ptr]
232 eor w18, w18, num_cpus
235 /* We need to walk swapper, so turn off the MMU. */
237 bic x18, x18, #SCTLR_ELx_M
241 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
243 mov cur_pgdp, swapper_pa
244 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
245 do_pgd: __idmap_kpti_get_pgtable_ent pgd
246 tbnz pgd, #1, walk_puds
248 __idmap_kpti_put_pgtable_ent_ng pgd
250 add cur_pgdp, cur_pgdp, #8
251 cmp cur_pgdp, end_pgdp
254 /* Publish the updated tables and nuke all the TLBs */
260 /* We're done: fire up the MMU again */
262 orr x18, x18, #SCTLR_ELx_M
266 /* Set the flag to zero to indicate that we're all done */
272 .if CONFIG_PGTABLE_LEVELS > 3
273 pte_to_phys cur_pudp, pgd
274 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
275 do_pud: __idmap_kpti_get_pgtable_ent pud
276 tbnz pud, #1, walk_pmds
278 __idmap_kpti_put_pgtable_ent_ng pud
280 add cur_pudp, cur_pudp, 8
281 cmp cur_pudp, end_pudp
284 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
293 .if CONFIG_PGTABLE_LEVELS > 2
294 pte_to_phys cur_pmdp, pud
295 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
296 do_pmd: __idmap_kpti_get_pgtable_ent pmd
297 tbnz pmd, #1, walk_ptes
299 __idmap_kpti_put_pgtable_ent_ng pmd
301 add cur_pmdp, cur_pmdp, #8
302 cmp cur_pmdp, end_pmdp
305 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
314 pte_to_phys cur_ptep, pmd
315 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
316 do_pte: __idmap_kpti_get_pgtable_ent pte
317 __idmap_kpti_put_pgtable_ent_ng pte
319 add cur_ptep, cur_ptep, #8
320 cmp cur_ptep, end_ptep
324 /* Secondary CPUs end up here */
325 __idmap_kpti_secondary:
326 /* Uninstall swapper before surgery begins */
327 __idmap_cpu_set_reserved_ttbr1 x18, x17
329 /* Increment the flag to let the boot CPU we're ready */
330 1: ldxr w18, [flag_ptr]
332 stxr w17, w18, [flag_ptr]
335 /* Wait for the boot CPU to finish messing around with swapper */
341 /* All done, act like nothing happened */
342 msr ttbr1_el1, swapper_ttb
363 ENDPROC(idmap_kpti_install_ng_mappings)
370 * Initialise the processor for turning the MMU on. Return in x0 the
371 * value of the SCTLR_EL1 register.
373 .pushsection ".idmap.text", "awx"
375 tlbi vmalle1 // Invalidate local TLB
379 msr cpacr_el1, x0 // Enable FP/ASIMD
380 mov x0, #1 << 12 // Reset mdscr_el1 and disable
381 msr mdscr_el1, x0 // access to the DCC from EL0
382 isb // Unmask debug exceptions now,
383 enable_dbg // since this is per-cpu
384 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
386 * Memory region attributes for LPAE:
390 * DEVICE_nGnRnE 000 00000000
391 * DEVICE_nGnRE 001 00000100
392 * DEVICE_GRE 010 00001100
393 * NORMAL_NC 011 01000100
394 * NORMAL 100 11111111
395 * NORMAL_WT 101 10111011
397 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
398 MAIR(0x04, MT_DEVICE_nGnRE) | \
399 MAIR(0x0c, MT_DEVICE_GRE) | \
400 MAIR(0x44, MT_NORMAL_NC) | \
401 MAIR(0xff, MT_NORMAL) | \
402 MAIR(0xbb, MT_NORMAL_WT)
410 bic x0, x0, x5 // clear bits
411 orr x0, x0, x6 // set bits
413 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
414 * both user and kernel.
416 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
417 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1
418 tcr_set_idmap_t0sz x10, x9
421 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
424 mrs x9, ID_AA64MMFR0_EL1
426 #ifdef CONFIG_ARM64_HW_AFDBM
428 * Hardware update of the Access and Dirty bits.
430 mrs x9, ID_AA64MMFR1_EL1
435 #ifdef CONFIG_ARM64_ERRATUM_1024718
436 /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */
437 cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(1, 0), x1, x2, x3, x4
440 orr x10, x10, #TCR_HD // hardware Dirty flag update
441 1: orr x10, x10, #TCR_HA // hardware Access flag update
443 #endif /* CONFIG_ARM64_HW_AFDBM */
445 ret // return to head.S
449 * We set the desired value explicitly, including those of the
450 * reserved bits. The values of bits EE & E0E were set early in
451 * el2_setup, which are left untouched below.
454 * U E WT T UD US IHBS
455 * CE0 XWHW CZ ME TEEA S
456 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
457 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
458 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
462 .word 0xfcffffff // clear
463 .word 0x34d5d91d // set