2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
32 #include <asm/memory.h>
33 #include <asm/thread_info.h>
34 #include <asm/pgtable-hwdef.h>
35 #include <asm/pgtable.h>
39 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
41 #if (TEXT_OFFSET & 0xfff) != 0
42 #error TEXT_OFFSET must be at least 4KB aligned
43 #elif (PAGE_OFFSET & 0x1fffff) != 0
44 #error PAGE_OFFSET must be at least 2MB aligned
45 #elif TEXT_OFFSET > 0x1fffff
46 #error TEXT_OFFSET must be less than 2MB
49 .macro pgtbl, ttb0, ttb1, virt_to_phys
50 ldr \ttb1, =swapper_pg_dir
51 ldr \ttb0, =idmap_pg_dir
52 add \ttb1, \ttb1, \virt_to_phys
53 add \ttb0, \ttb0, \virt_to_phys
56 #ifdef CONFIG_ARM64_64K_PAGES
57 #define BLOCK_SHIFT PAGE_SHIFT
58 #define BLOCK_SIZE PAGE_SIZE
59 #define TABLE_SHIFT PMD_SHIFT
61 #define BLOCK_SHIFT SECTION_SHIFT
62 #define BLOCK_SIZE SECTION_SIZE
63 #define TABLE_SHIFT PUD_SHIFT
66 #define KERNEL_START KERNEL_RAM_VADDR
67 #define KERNEL_END _end
70 * Initial memory map attributes.
73 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
74 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
76 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
77 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
80 #ifdef CONFIG_ARM64_64K_PAGES
81 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
83 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
87 * Kernel startup entry point.
88 * ---------------------------
90 * The requirements are:
91 * MMU = off, D-cache = off, I-cache = on or off,
92 * x0 = physical address to the FDT blob.
94 * This code is mostly position independent so you call this at
95 * __pa(PAGE_OFFSET + TEXT_OFFSET).
97 * Note that the callee-saved registers are used for storing variables
98 * that are useful before the MMU is enabled. The allocations are described
99 * in the entry routines.
104 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
109 * This add instruction has no meaningful effect except that
110 * its opcode forms the magic "MZ" signature required by UEFI.
115 b stext // branch to kernel start, magic
118 .quad _kernel_offset_le // Image load offset from start of RAM, little-endian
119 .quad _kernel_size_le // Effective size of kernel image, little-endian
120 .quad _kernel_flags_le // Informative flags, little-endian
124 .byte 0x41 // Magic number, "ARM\x64"
129 .long pe_header - efi_head // Offset to the PE header.
140 .short 0xaa64 // AArch64
141 .short 2 // nr_sections
142 .long 0 // TimeDateStamp
143 .long 0 // PointerToSymbolTable
144 .long 1 // NumberOfSymbols
145 .short section_table - optional_header // SizeOfOptionalHeader
146 .short 0x206 // Characteristics.
147 // IMAGE_FILE_DEBUG_STRIPPED |
148 // IMAGE_FILE_EXECUTABLE_IMAGE |
149 // IMAGE_FILE_LINE_NUMS_STRIPPED
151 .short 0x20b // PE32+ format
152 .byte 0x02 // MajorLinkerVersion
153 .byte 0x14 // MinorLinkerVersion
154 .long _end - stext // SizeOfCode
155 .long 0 // SizeOfInitializedData
156 .long 0 // SizeOfUninitializedData
157 .long efi_stub_entry - efi_head // AddressOfEntryPoint
158 .long stext - efi_head // BaseOfCode
162 .long 0x20 // SectionAlignment
163 .long 0x8 // FileAlignment
164 .short 0 // MajorOperatingSystemVersion
165 .short 0 // MinorOperatingSystemVersion
166 .short 0 // MajorImageVersion
167 .short 0 // MinorImageVersion
168 .short 0 // MajorSubsystemVersion
169 .short 0 // MinorSubsystemVersion
170 .long 0 // Win32VersionValue
172 .long _end - efi_head // SizeOfImage
174 // Everything before the kernel image is considered part of the header
175 .long stext - efi_head // SizeOfHeaders
177 .short 0xa // Subsystem (EFI application)
178 .short 0 // DllCharacteristics
179 .quad 0 // SizeOfStackReserve
180 .quad 0 // SizeOfStackCommit
181 .quad 0 // SizeOfHeapReserve
182 .quad 0 // SizeOfHeapCommit
183 .long 0 // LoaderFlags
184 .long 0x6 // NumberOfRvaAndSizes
186 .quad 0 // ExportTable
187 .quad 0 // ImportTable
188 .quad 0 // ResourceTable
189 .quad 0 // ExceptionTable
190 .quad 0 // CertificationTable
191 .quad 0 // BaseRelocationTable
197 * The EFI application loader requires a relocation section
198 * because EFI applications must be relocatable. This is a
199 * dummy section as far as we are concerned.
203 .byte 0 // end of 0 padding of section name
206 .long 0 // SizeOfRawData
207 .long 0 // PointerToRawData
208 .long 0 // PointerToRelocations
209 .long 0 // PointerToLineNumbers
210 .short 0 // NumberOfRelocations
211 .short 0 // NumberOfLineNumbers
212 .long 0x42100040 // Characteristics (section flags)
218 .byte 0 // end of 0 padding of section name
219 .long _end - stext // VirtualSize
220 .long stext - efi_head // VirtualAddress
221 .long _edata - stext // SizeOfRawData
222 .long stext - efi_head // PointerToRawData
224 .long 0 // PointerToRelocations (0 for executables)
225 .long 0 // PointerToLineNumbers (0 for executables)
226 .short 0 // NumberOfRelocations (0 for executables)
227 .short 0 // NumberOfLineNumbers (0 for executables)
228 .long 0xe0500020 // Characteristics (section flags)
233 mov x21, x0 // x21=FDT
234 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
235 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
236 bl set_cpu_boot_mode_flag
237 mrs x22, midr_el1 // x22=cpuid
239 bl lookup_processor_type
240 mov x23, x0 // x23=current cpu_table
241 cbz x23, __error_p // invalid processor (x23=0)?
243 bl __create_page_tables // x25=TTBR0, x26=TTBR1
245 * The following calls CPU specific code in a position independent
246 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
247 * cpu_info structure selected by lookup_processor_type above.
248 * On return, the CPU will be ready for the MMU to be turned on and
249 * the TCR will have been set.
251 ldr x27, __switch_data // address to jump to after
252 // MMU has been enabled
253 adr lr, __enable_mmu // return (PIC) address
254 ldr x12, [x23, #CPU_INFO_SETUP]
255 add x12, x12, x28 // __virt_to_phys
256 br x12 // initialise processor
260 * If we're fortunate enough to boot at EL2, ensure that the world is
261 * sane before dropping to EL1.
263 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
264 * booted in EL1 or EL2 respectively.
267 msr SPsel, #1 // We want to use SP_EL{1,2}
269 cmp x0, #CurrentEL_EL2
272 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
273 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
277 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
278 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
280 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
284 /* Hyp configuration. */
285 2: mov x0, #(1 << 31) // 64-bit EL1
288 /* Generic timers. */
290 orr x0, x0, #3 // Enable EL1 physical timers
292 msr cntvoff_el2, xzr // Clear virtual offset
294 #ifdef CONFIG_ARM_GIC_V3
295 /* GICv3 system register access */
296 mrs x0, id_aa64pfr0_el1
301 mrs_s x0, ICC_SRE_EL2
302 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
303 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
304 msr_s ICC_SRE_EL2, x0
305 isb // Make sure SRE is now set
306 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
311 /* Populate ID registers. */
318 mov x0, #0x0800 // Set/clear RES{1,0} bits
319 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
320 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
323 /* Coprocessor traps. */
325 msr cptr_el2, x0 // Disable copro. traps to EL2
328 msr hstr_el2, xzr // Disable CP15 traps to EL2
332 mrs x0, pmcr_el0 // Disable debug access traps
333 ubfx x0, x0, #11, #5 // to EL2 and allow access to
334 msr mdcr_el2, x0 // all PMU counters from EL1
336 /* Stage-2 translation */
339 /* Hypervisor stub */
340 adr x0, __hyp_stub_vectors
344 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
348 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
353 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
354 * in x20. See arch/arm64/include/asm/virt.h for more info.
356 ENTRY(set_cpu_boot_mode_flag)
357 ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode
359 cmp w20, #BOOT_CPU_MODE_EL2
362 1: str w20, [x1] // This CPU has booted in EL1
364 dc ivac, x1 // Invalidate potentially stale cache line
366 ENDPROC(set_cpu_boot_mode_flag)
369 * We need to find out the CPU boot mode long after boot, so we need to
370 * store it in a writable variable.
372 * This is not in .bss, because we set it sufficiently early that the boot-time
373 * zeroing of .bss would clobber it.
375 .pushsection .data..cacheline_aligned
376 ENTRY(__boot_cpu_mode)
377 .align L1_CACHE_SHIFT
378 .long BOOT_CPU_MODE_EL2
385 .quad secondary_holding_pen_release
388 * This provides a "holding pen" for platforms to hold all secondary
389 * cores are held until we're ready for them to initialise.
391 ENTRY(secondary_holding_pen)
392 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
393 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
394 bl set_cpu_boot_mode_flag
396 ldr x1, =MPIDR_HWID_BITMASK
404 b.eq secondary_startup
407 ENDPROC(secondary_holding_pen)
410 * Secondary entry point that jumps straight into the kernel. Only to
411 * be used where CPUs are brought online dynamically by the kernel.
413 ENTRY(secondary_entry)
414 bl el2_setup // Drop to EL1
415 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
416 bl set_cpu_boot_mode_flag
418 ENDPROC(secondary_entry)
420 ENTRY(secondary_startup)
422 * Common entry point for secondary CPUs.
424 mrs x22, midr_el1 // x22=cpuid
426 bl lookup_processor_type
427 mov x23, x0 // x23=current cpu_table
428 cbz x23, __error_p // invalid processor (x23=0)?
430 pgtbl x25, x26, x28 // x25=TTBR0, x26=TTBR1
431 ldr x12, [x23, #CPU_INFO_SETUP]
432 add x12, x12, x28 // __virt_to_phys
433 blr x12 // initialise processor
435 ldr x21, =secondary_data
436 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
438 ENDPROC(secondary_startup)
440 ENTRY(__secondary_switched)
441 ldr x0, [x21] // get secondary_data.stack
444 b secondary_start_kernel
445 ENDPROC(__secondary_switched)
446 #endif /* CONFIG_SMP */
449 * Setup common bits before finally enabling the MMU. Essentially this is just
450 * loading the page table pointer and vector base registers.
452 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
458 msr ttbr0_el1, x25 // load TTBR0
459 msr ttbr1_el1, x26 // load TTBR1
462 ENDPROC(__enable_mmu)
465 * Enable the MMU. This completely changes the structure of the visible memory
466 * space. You will not be able to trace execution through this.
468 * x0 = system control register
469 * x27 = *virtual* address to jump to upon completion
471 * other registers depend on the function called upon completion
473 * We align the entire function to the smallest power of two larger than it to
474 * ensure it fits within a single block map entry. Otherwise were PHYS_OFFSET
475 * close to the end of a 512MB or 1GB block we might require an additional
476 * table to map the entire function.
483 ENDPROC(__turn_mmu_on)
486 * Calculate the start of physical memory.
491 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
492 add x24, x2, x28 // x24 = PHYS_OFFSET
494 ENDPROC(__calc_phys_offset)
501 * Macro to create a table entry to the next page.
503 * tbl: page table address
504 * virt: virtual address
505 * shift: #imm page table shift
506 * ptrs: #imm pointers per table page
509 * Corrupts: tmp1, tmp2
510 * Returns: tbl -> next level table page address
512 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
513 lsr \tmp1, \virt, #\shift
514 and \tmp1, \tmp1, #\ptrs - 1 // table index
515 add \tmp2, \tbl, #PAGE_SIZE
516 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
517 str \tmp2, [\tbl, \tmp1, lsl #3]
518 add \tbl, \tbl, #PAGE_SIZE // next level table page
522 * Macro to populate the PGD (and possibily PUD) for the corresponding
523 * block entry in the next level (tbl) for the given virtual address.
525 * Preserves: tbl, next, virt
526 * Corrupts: tmp1, tmp2
528 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
529 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
530 #if SWAPPER_PGTABLE_LEVELS == 3
531 create_table_entry \tbl, \virt, TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
536 * Macro to populate block entries in the page table for the start..end
537 * virtual range (inclusive).
539 * Preserves: tbl, flags
540 * Corrupts: phys, start, end, pstate
542 .macro create_block_map, tbl, flags, phys, start, end
543 lsr \phys, \phys, #BLOCK_SHIFT
544 lsr \start, \start, #BLOCK_SHIFT
545 and \start, \start, #PTRS_PER_PTE - 1 // table index
546 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
547 lsr \end, \end, #BLOCK_SHIFT
548 and \end, \end, #PTRS_PER_PTE - 1 // table end index
549 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
550 add \start, \start, #1 // next entry
551 add \phys, \phys, #BLOCK_SIZE // next block
557 * Setup the initial page tables. We only setup the barest amount which is
558 * required to get the kernel running. The following sections are required:
559 * - identity mapping to enable the MMU (low address, TTBR0)
560 * - first few MB of the kernel linear mapping to jump to once the MMU has
561 * been enabled, including the FDT blob (TTBR1)
562 * - pgd entry for fixed mappings (TTBR1)
564 __create_page_tables:
565 pgtbl x25, x26, x28 // idmap_pg_dir and swapper_pg_dir addresses
569 * Invalidate the idmap and swapper page tables to avoid potential
570 * dirty cache lines being evicted.
573 add x1, x26, #SWAPPER_DIR_SIZE
574 bl __inval_cache_range
577 * Clear the idmap and swapper page tables.
580 add x6, x26, #SWAPPER_DIR_SIZE
581 1: stp xzr, xzr, [x0], #16
582 stp xzr, xzr, [x0], #16
583 stp xzr, xzr, [x0], #16
584 stp xzr, xzr, [x0], #16
591 * Create the identity mapping.
593 mov x0, x25 // idmap_pg_dir
594 ldr x3, =KERNEL_START
595 add x3, x3, x28 // __pa(KERNEL_START)
596 create_pgd_entry x0, x3, x5, x6
598 mov x5, x3 // __pa(KERNEL_START)
599 add x6, x6, x28 // __pa(KERNEL_END)
600 create_block_map x0, x7, x3, x5, x6
603 * Map the kernel image (starting with PHYS_OFFSET).
605 mov x0, x26 // swapper_pg_dir
607 create_pgd_entry x0, x5, x3, x6
609 mov x3, x24 // phys offset
610 create_block_map x0, x7, x3, x5, x6
613 * Map the FDT blob (maximum 2MB; must be within 512MB of
616 mov x3, x21 // FDT phys address
617 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
619 sub x5, x3, x24 // subtract PHYS_OFFSET
620 tst x5, #~((1 << 29) - 1) // within 512MB?
621 csel x21, xzr, x21, ne // zero the FDT pointer
623 add x5, x5, x6 // __va(FDT blob)
624 add x6, x5, #1 << 21 // 2MB for the FDT blob
625 sub x6, x6, #1 // inclusive range
626 create_block_map x0, x7, x3, x5, x6
629 * Since the page tables have been populated with non-cacheable
630 * accesses (MMU disabled), invalidate the idmap and swapper page
631 * tables again to remove any speculatively loaded cache lines.
634 add x1, x26, #SWAPPER_DIR_SIZE
635 bl __inval_cache_range
639 ENDPROC(__create_page_tables)
643 .type __switch_data, %object
645 .quad __mmap_switched
646 .quad __bss_start // x6
647 .quad __bss_stop // x7
648 .quad processor_id // x4
649 .quad __fdt_pointer // x5
650 .quad memstart_addr // x6
651 .quad init_thread_union + THREAD_START_SP // sp
654 * The following fragment of code is executed with the MMU on in MMU mode, and
655 * uses absolute addresses; this is not position independent.
658 adr x3, __switch_data + 8
660 ldp x6, x7, [x3], #16
663 str xzr, [x6], #8 // Clear BSS
666 ldp x4, x5, [x3], #16
670 str x22, [x4] // Save processor ID
671 str x21, [x5] // Save FDT pointer
672 str x24, [x6] // Save PHYS_OFFSET
675 ENDPROC(__mmap_switched)
678 * Exception handling. Something went wrong and we can't proceed. We ought to
679 * tell the user, but since we don't have any guarantee that we're even
680 * running on the right architecture, we do virtually nothing.
691 * This function gets the processor ID in w0 and searches the cpu_table[] for
692 * a match. It returns a pointer to the struct cpu_info it found. The
693 * cpu_table[] must end with an empty (all zeros) structure.
695 * This routine can be called via C code and it needs to work with the MMU
696 * both disabled and enabled (the offset is calculated automatically).
698 ENTRY(lookup_processor_type)
699 adr x1, __lookup_processor_type_data
701 sub x1, x1, x2 // get offset between VA and PA
702 add x3, x3, x1 // convert VA to PA
704 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
705 cbz w5, 2f // end of list?
709 add x3, x3, #CPU_INFO_SZ
712 mov x3, #0 // unknown processor
716 ENDPROC(lookup_processor_type)
719 .type __lookup_processor_type_data, %object
720 __lookup_processor_type_data:
723 .size __lookup_processor_type_data, . - __lookup_processor_type_data
726 * Determine validity of the x21 FDT pointer.
727 * The dtb must be 8-byte aligned and live in the first 512M of memory.