arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-j721e.dtsi"
   9
  10 / {
  11         memory@80000000 {
  12                 device_type = "memory";
  13                 /* 4G RAM */
  14                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  15                       <0x00000008 0x80000000 0x00000000 0x80000000>;
  16         };
  17
  18         reserved_memory: reserved-memory {
  19                 #address-cells = <2>;
  20                 #size-cells = <2>;
  21                 ranges;
  22
  23                 secure_ddr: optee@9e800000 {
  24                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  25                         alignment = <0x1000>;
  26                         no-map;
  27                 };
  28         };
  29 };
  30
  31 &wkup_pmx0 {
  32         wkup_i2c0_pins_default: wkup_i2c0_pins_default {
  33                 pinctrl-single,pins = <
  34                         J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
  35                         J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
  36                 >;
  37         };
  38
  39         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
  40                 pinctrl-single,pins = <
  41                         J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
  42                         J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
  43                         J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
  44                         J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
  45                         J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
  46                         J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
  47                         J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
  48                         J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
  49                         J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
  50                         J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
  51                         J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
  52                 >;
  53         };
  54 };
  55
  56 &ospi0 {
  57         pinctrl-names = "default";
  58         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
  59
  60         flash@0{
  61                 compatible = "jedec,spi-nor";
  62                 reg = <0x0>;
  63                 spi-tx-bus-width = <1>;
  64                 spi-rx-bus-width = <8>;
  65                 spi-max-frequency = <40000000>;
  66                 cdns,tshsl-ns = <60>;
  67                 cdns,tsd2d-ns = <60>;
  68                 cdns,tchsh-ns = <60>;
  69                 cdns,tslch-ns = <60>;
  70                 cdns,read-delay = <0>;
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73         };
  74 };