arch/arm64/boot/dts/intel/socfpga_agilex.dtsi

   1 // SPDX-License-Identifier:     GPL-2.0
   2 /*
   3  * Copyright (C) 2019, Intel Corporation
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         compatible = "intel,socfpga-agilex";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a53";
  21                         device_type = "cpu";
  22                         enable-method = "psci";
  23                         reg = <0x0>;
  24                 };
  25
  26                 cpu1: cpu@1 {
  27                         compatible = "arm,cortex-a53";
  28                         device_type = "cpu";
  29                         enable-method = "psci";
  30                         reg = <0x1>;
  31                 };
  32
  33                 cpu2: cpu@2 {
  34                         compatible = "arm,cortex-a53";
  35                         device_type = "cpu";
  36                         enable-method = "psci";
  37                         reg = <0x2>;
  38                 };
  39
  40                 cpu3: cpu@3 {
  41                         compatible = "arm,cortex-a53";
  42                         device_type = "cpu";
  43                         enable-method = "psci";
  44                         reg = <0x3>;
  45                 };
  46         };
  47
  48         pmu {
  49                 compatible = "arm,armv8-pmuv3";
  50                 interrupts = <0 120 8>,
  51                              <0 121 8>,
  52                              <0 122 8>,
  53                              <0 123 8>;
  54                 interrupt-affinity = <&cpu0>,
  55                                      <&cpu1>,
  56                                      <&cpu2>,
  57                                      <&cpu3>;
  58                 interrupt-parent = <&intc>;
  59         };
  60
  61         psci {
  62                 compatible = "arm,psci-0.2";
  63                 method = "smc";
  64         };
  65
  66         intc: intc@fffc1000 {
  67                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  68                 #interrupt-cells = <3>;
  69                 interrupt-controller;
  70                 reg = <0x0 0xfffc1000 0x0 0x1000>,
  71                       <0x0 0xfffc2000 0x0 0x2000>,
  72                       <0x0 0xfffc4000 0x0 0x2000>,
  73                       <0x0 0xfffc6000 0x0 0x2000>;
  74         };
  75
  76         soc {
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 compatible = "simple-bus";
  80                 device_type = "soc";
  81                 interrupt-parent = <&intc>;
  82                 ranges = <0 0 0 0xffffffff>;
  83
  84                 gmac0: ethernet@ff800000 {
  85                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
  86                         reg = <0xff800000 0x2000>;
  87                         interrupts = <0 90 4>;
  88                         interrupt-names = "macirq";
  89                         mac-address = [00 00 00 00 00 00];
  90                         resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
  91                         reset-names = "stmmaceth", "stmmaceth-ocp";
  92                         tx-fifo-depth = <16384>;
  93                         rx-fifo-depth = <16384>;
  94                         snps,multicast-filter-bins = <256>;
  95                         iommus = <&smmu 1>;
  96                         status = "disabled";
  97                 };
  98
  99                 gmac1: ethernet@ff802000 {
 100                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 101                         reg = <0xff802000 0x2000>;
 102                         interrupts = <0 91 4>;
 103                         interrupt-names = "macirq";
 104                         mac-address = [00 00 00 00 00 00];
 105                         resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 106                         reset-names = "stmmaceth", "stmmaceth-ocp";
 107                         tx-fifo-depth = <16384>;
 108                         rx-fifo-depth = <16384>;
 109                         snps,multicast-filter-bins = <256>;
 110                         iommus = <&smmu 2>;
 111                         status = "disabled";
 112                 };
 113
 114                 gmac2: ethernet@ff804000 {
 115                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 116                         reg = <0xff804000 0x2000>;
 117                         interrupts = <0 92 4>;
 118                         interrupt-names = "macirq";
 119                         mac-address = [00 00 00 00 00 00];
 120                         resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 121                         reset-names = "stmmaceth", "stmmaceth-ocp";
 122                         tx-fifo-depth = <16384>;
 123                         rx-fifo-depth = <16384>;
 124                         snps,multicast-filter-bins = <256>;
 125                         iommus = <&smmu 3>;
 126                         status = "disabled";
 127                 };
 128
 129                 gpio0: gpio@ffc03200 {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         compatible = "snps,dw-apb-gpio";
 133                         reg = <0xffc03200 0x100>;
 134                         resets = <&rst GPIO0_RESET>;
 135                         status = "disabled";
 136
 137                         porta: gpio-controller@0 {
 138                                 compatible = "snps,dw-apb-gpio-port";
 139                                 gpio-controller;
 140                                 #gpio-cells = <2>;
 141                                 snps,nr-gpios = <24>;
 142                                 reg = <0>;
 143                                 interrupt-controller;
 144                                 #interrupt-cells = <2>;
 145                                 interrupts = <0 110 4>;
 146                         };
 147                 };
 148
 149                 gpio1: gpio@ffc03300 {
 150                         #address-cells = <1>;
 151                         #size-cells = <0>;
 152                         compatible = "snps,dw-apb-gpio";
 153                         reg = <0xffc03300 0x100>;
 154                         resets = <&rst GPIO1_RESET>;
 155                         status = "disabled";
 156
 157                         portb: gpio-controller@0 {
 158                                 compatible = "snps,dw-apb-gpio-port";
 159                                 gpio-controller;
 160                                 #gpio-cells = <2>;
 161                                 snps,nr-gpios = <24>;
 162                                 reg = <0>;
 163                                 interrupt-controller;
 164                                 #interrupt-cells = <2>;
 165                                 interrupts = <0 111 4>;
 166                         };
 167                 };
 168
 169                 i2c0: i2c@ffc02800 {
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         compatible = "snps,designware-i2c";
 173                         reg = <0xffc02800 0x100>;
 174                         interrupts = <0 103 4>;
 175                         resets = <&rst I2C0_RESET>;
 176                         status = "disabled";
 177                 };
 178
 179                 i2c1: i2c@ffc02900 {
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         compatible = "snps,designware-i2c";
 183                         reg = <0xffc02900 0x100>;
 184                         interrupts = <0 104 4>;
 185                         resets = <&rst I2C1_RESET>;
 186                         status = "disabled";
 187                 };
 188
 189                 i2c2: i2c@ffc02a00 {
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192                         compatible = "snps,designware-i2c";
 193                         reg = <0xffc02a00 0x100>;
 194                         interrupts = <0 105 4>;
 195                         resets = <&rst I2C2_RESET>;
 196                         status = "disabled";
 197                 };
 198
 199                 i2c3: i2c@ffc02b00 {
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         compatible = "snps,designware-i2c";
 203                         reg = <0xffc02b00 0x100>;
 204                         interrupts = <0 106 4>;
 205                         resets = <&rst I2C3_RESET>;
 206                         status = "disabled";
 207                 };
 208
 209                 i2c4: i2c@ffc02c00 {
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                         compatible = "snps,designware-i2c";
 213                         reg = <0xffc02c00 0x100>;
 214                         interrupts = <0 107 4>;
 215                         resets = <&rst I2C4_RESET>;
 216                         status = "disabled";
 217                 };
 218
 219                 mmc: dwmmc0@ff808000 {
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         compatible = "altr,socfpga-dw-mshc";
 223                         reg = <0xff808000 0x1000>;
 224                         interrupts = <0 96 4>;
 225                         fifo-depth = <0x400>;
 226                         resets = <&rst SDMMC_RESET>;
 227                         reset-names = "reset";
 228                         iommus = <&smmu 5>;
 229                         status = "disabled";
 230                 };
 231
 232                 ocram: sram@ffe00000 {
 233                         compatible = "mmio-sram";
 234                         reg = <0xffe00000 0x40000>;
 235                 };
 236
 237                 pdma: pdma@ffda0000 {
 238                         compatible = "arm,pl330", "arm,primecell";
 239                         reg = <0xffda0000 0x1000>;
 240                         interrupts = <0 81 4>,
 241                                      <0 82 4>,
 242                                      <0 83 4>,
 243                                      <0 84 4>,
 244                                      <0 85 4>,
 245                                      <0 86 4>,
 246                                      <0 87 4>,
 247                                      <0 88 4>,
 248                                      <0 89 4>;
 249                         #dma-cells = <1>;
 250                         #dma-channels = <8>;
 251                         #dma-requests = <32>;
 252                 };
 253
 254                 rst: rstmgr@ffd11000 {
 255                         #reset-cells = <1>;
 256                         compatible = "altr,stratix10-rst-mgr";
 257                         reg = <0xffd11000 0x100>;
 258                 };
 259
 260                 smmu: iommu@fa000000 {
 261                         compatible = "arm,mmu-500", "arm,smmu-v2";
 262                         reg = <0xfa000000 0x40000>;
 263                         #global-interrupts = <2>;
 264                         #iommu-cells = <1>;
 265                         interrupt-parent = <&intc>;
 266                         interrupts = <0 128 4>, /* Global Secure Fault */
 267                                 <0 129 4>, /* Global Non-secure Fault */
 268                                 /* Non-secure Context Interrupts (32) */
 269                                 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
 270                                 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
 271                                 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
 272                                 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
 273                                 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
 274                                 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
 275                                 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
 276                                 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
 277                         stream-match-mask = <0x7ff0>;
 278                         status = "disabled";
 279                 };
 280
 281                 spi0: spi@ffda4000 {
 282                         compatible = "snps,dw-apb-ssi";
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         reg = <0xffda4000 0x1000>;
 286                         interrupts = <0 99 4>;
 287                         resets = <&rst SPIM0_RESET>;
 288                         reg-io-width = <4>;
 289                         num-cs = <4>;
 290                         status = "disabled";
 291                 };
 292
 293                 spi1: spi@ffda5000 {
 294                         compatible = "snps,dw-apb-ssi";
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         reg = <0xffda5000 0x1000>;
 298                         interrupts = <0 100 4>;
 299                         resets = <&rst SPIM1_RESET>;
 300                         reg-io-width = <4>;
 301                         num-cs = <4>;
 302                         status = "disabled";
 303                 };
 304
 305                 sysmgr: sysmgr@ffd12000 {
 306                         compatible = "altr,sys-mgr", "syscon";
 307                         reg = <0xffd12000 0x500>;
 308                 };
 309
 310                 /* Local timer */
 311                 timer {
 312                         compatible = "arm,armv8-timer";
 313                         interrupts = <1 13 0xf08>,
 314                                      <1 14 0xf08>,
 315                                      <1 11 0xf08>,
 316                                      <1 10 0xf08>;
 317                 };
 318
 319                 timer0: timer0@ffc03000 {
 320                         compatible = "snps,dw-apb-timer";
 321                         interrupts = <0 113 4>;
 322                         reg = <0xffc03000 0x100>;
 323                 };
 324
 325                 timer1: timer1@ffc03100 {
 326                         compatible = "snps,dw-apb-timer";
 327                         interrupts = <0 114 4>;
 328                         reg = <0xffc03100 0x100>;
 329                 };
 330
 331                 timer2: timer2@ffd00000 {
 332                         compatible = "snps,dw-apb-timer";
 333                         interrupts = <0 115 4>;
 334                         reg = <0xffd00000 0x100>;
 335                 };
 336
 337                 timer3: timer3@ffd00100 {
 338                         compatible = "snps,dw-apb-timer";
 339                         interrupts = <0 116 4>;
 340                         reg = <0xffd00100 0x100>;
 341                 };
 342
 343                 uart0: serial0@ffc02000 {
 344                         compatible = "snps,dw-apb-uart";
 345                         reg = <0xffc02000 0x100>;
 346                         interrupts = <0 108 4>;
 347                         reg-shift = <2>;
 348                         reg-io-width = <4>;
 349                         resets = <&rst UART0_RESET>;
 350                         status = "disabled";
 351                 };
 352
 353                 uart1: serial1@ffc02100 {
 354                         compatible = "snps,dw-apb-uart";
 355                         reg = <0xffc02100 0x100>;
 356                         interrupts = <0 109 4>;
 357                         reg-shift = <2>;
 358                         reg-io-width = <4>;
 359                         resets = <&rst UART1_RESET>;
 360                         status = "disabled";
 361                 };
 362
 363                 usbphy0: usbphy@0 {
 364                         #phy-cells = <0>;
 365                         compatible = "usb-nop-xceiv";
 366                         status = "okay";
 367                 };
 368
 369                 usb0: usb@ffb00000 {
 370                         compatible = "snps,dwc2";
 371                         reg = <0xffb00000 0x40000>;
 372                         interrupts = <0 93 4>;
 373                         phys = <&usbphy0>;
 374                         phy-names = "usb2-phy";
 375                         resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 376                         reset-names = "dwc2", "dwc2-ecc";
 377                         iommus = <&smmu 6>;
 378                         status = "disabled";
 379                 };
 380
 381                 usb1: usb@ffb40000 {
 382                         compatible = "snps,dwc2";
 383                         reg = <0xffb40000 0x40000>;
 384                         interrupts = <0 94 4>;
 385                         phys = <&usbphy0>;
 386                         phy-names = "usb2-phy";
 387                         resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
 388                         reset-names = "dwc2", "dwc2-ecc";
 389                         iommus = <&smmu 7>;
 390                         status = "disabled";
 391                 };
 392
 393                 watchdog0: watchdog@ffd00200 {
 394                         compatible = "snps,dw-wdt";
 395                         reg = <0xffd00200 0x100>;
 396                         interrupts = <0 117 4>;
 397                         resets = <&rst WATCHDOG0_RESET>;
 398                         status = "disabled";
 399                 };
 400
 401                 watchdog1: watchdog@ffd00300 {
 402                         compatible = "snps,dw-wdt";
 403                         reg = <0xffd00300 0x100>;
 404                         interrupts = <0 118 4>;
 405                         resets = <&rst WATCHDOG1_RESET>;
 406                         status = "disabled";
 407                 };
 408
 409                 watchdog2: watchdog@ffd00400 {
 410                         compatible = "snps,dw-wdt";
 411                         reg = <0xffd00400 0x100>;
 412                         interrupts = <0 125 4>;
 413                         resets = <&rst WATCHDOG2_RESET>;
 414                         status = "disabled";
 415                 };
 416
 417                 watchdog3: watchdog@ffd00500 {
 418                         compatible = "snps,dw-wdt";
 419                         reg = <0xffd00500 0x100>;
 420                         interrupts = <0 126 4>;
 421                         resets = <&rst WATCHDOG3_RESET>;
 422                         status = "disabled";
 423                 };
 424
 425                 sdr: sdr@f8011100 {
 426                         compatible = "altr,sdr-ctl", "syscon";
 427                         reg = <0xf8011100 0xc0>;
 428                 };
 429
 430                 qspi: spi@ff8d2000 {
 431                         compatible = "cdns,qspi-nor";
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         reg = <0xff8d2000 0x100>,
 435                               <0xff900000 0x100000>;
 436                         interrupts = <0 3 4>;
 437                         cdns,fifo-depth = <128>;
 438                         cdns,fifo-width = <4>;
 439                         cdns,trigger-address = <0x00000000>;
 440
 441                         status = "disabled";
 442                 };
 443         };
 444 };