arch/arm64/boot/dts/freescale/imx8mm.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mm-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 #include "imx8mm-pinfunc.h"
  13
  14 / {
  15         compatible = "fsl,imx8mm";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 ethernet0 = &fec1;
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 i2c3 = &i2c4;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 spi0 = &ecspi1;
  31                 spi1 = &ecspi2;
  32                 spi2 = &ecspi3;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 gpio0 = &gpio1;
  37                 gpio1 = &gpio2;
  38                 gpio2 = &gpio3;
  39                 gpio3 = &gpio4;
  40                 gpio4 = &gpio5;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 A53_0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         reg = <0x0>;
  51                         clock-latency = <61036>; /* two CLK32 periods */
  52                         clocks = <&clk IMX8MM_CLK_ARM>;
  53                         enable-method = "psci";
  54                         next-level-cache = <&A53_L2>;
  55                         operating-points-v2 = <&a53_opp_table>;
  56                         nvmem-cells = <&cpu_speed_grade>;
  57                         nvmem-cell-names = "speed_grade";
  58                 };
  59
  60                 A53_1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         reg = <0x1>;
  64                         clock-latency = <61036>; /* two CLK32 periods */
  65                         clocks = <&clk IMX8MM_CLK_ARM>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&A53_L2>;
  68                         operating-points-v2 = <&a53_opp_table>;
  69                 };
  70
  71                 A53_2: cpu@2 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x2>;
  75                         clock-latency = <61036>; /* two CLK32 periods */
  76                         clocks = <&clk IMX8MM_CLK_ARM>;
  77                         enable-method = "psci";
  78                         next-level-cache = <&A53_L2>;
  79                         operating-points-v2 = <&a53_opp_table>;
  80                 };
  81
  82                 A53_3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         reg = <0x3>;
  86                         clock-latency = <61036>; /* two CLK32 periods */
  87                         clocks = <&clk IMX8MM_CLK_ARM>;
  88                         enable-method = "psci";
  89                         next-level-cache = <&A53_L2>;
  90                         operating-points-v2 = <&a53_opp_table>;
  91                 };
  92
  93                 A53_L2: l2-cache0 {
  94                         compatible = "cache";
  95                 };
  96         };
  97
  98         a53_opp_table: opp-table {
  99                 compatible = "operating-points-v2";
 100                 opp-shared;
 101
 102                 opp-1200000000 {
 103                         opp-hz = /bits/ 64 <1200000000>;
 104                         opp-microvolt = <850000>;
 105                         opp-supported-hw = <0xe>, <0x7>;
 106                         clock-latency-ns = <150000>;
 107                 };
 108
 109                 opp-1600000000 {
 110                         opp-hz = /bits/ 64 <1600000000>;
 111                         opp-microvolt = <900000>;
 112                         opp-supported-hw = <0xc>, <0x7>;
 113                         clock-latency-ns = <150000>;
 114                 };
 115
 116                 opp-1800000000 {
 117                         opp-hz = /bits/ 64 <1800000000>;
 118                         opp-microvolt = <1000000>;
 119                         /* Consumer only but rely on speed grading */
 120                         opp-supported-hw = <0x8>, <0x7>;
 121                         clock-latency-ns = <150000>;
 122                 };
 123         };
 124
 125         memory@40000000 {
 126                 device_type = "memory";
 127                 reg = <0x0 0x40000000 0 0x80000000>;
 128         };
 129
 130         osc_32k: clock-osc-32k {
 131                 compatible = "fixed-clock";
 132                 #clock-cells = <0>;
 133                 clock-frequency = <32768>;
 134                 clock-output-names = "osc_32k";
 135         };
 136
 137         osc_24m: clock-osc-24m {
 138                 compatible = "fixed-clock";
 139                 #clock-cells = <0>;
 140                 clock-frequency = <24000000>;
 141                 clock-output-names = "osc_24m";
 142         };
 143
 144         clk_ext1: clock-ext1 {
 145                 compatible = "fixed-clock";
 146                 #clock-cells = <0>;
 147                 clock-frequency = <133000000>;
 148                 clock-output-names = "clk_ext1";
 149         };
 150
 151         clk_ext2: clock-ext2 {
 152                 compatible = "fixed-clock";
 153                 #clock-cells = <0>;
 154                 clock-frequency = <133000000>;
 155                 clock-output-names = "clk_ext2";
 156         };
 157
 158         clk_ext3: clock-ext3 {
 159                 compatible = "fixed-clock";
 160                 #clock-cells = <0>;
 161                 clock-frequency = <133000000>;
 162                 clock-output-names = "clk_ext3";
 163         };
 164
 165         clk_ext4: clock-ext4 {
 166                 compatible = "fixed-clock";
 167                 #clock-cells = <0>;
 168                 clock-frequency= <133000000>;
 169                 clock-output-names = "clk_ext4";
 170         };
 171
 172         psci {
 173                 compatible = "arm,psci-1.0";
 174                 method = "smc";
 175         };
 176
 177         pmu {
 178                 compatible = "arm,armv8-pmuv3";
 179                 interrupts = <GIC_PPI 7
 180                              (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 181                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 182         };
 183
 184         timer {
 185                 compatible = "arm,armv8-timer";
 186                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
 187                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
 188                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
 189                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
 190                 clock-frequency = <8000000>;
 191                 arm,no-tick-in-suspend;
 192         };
 193
 194         usbphynop1: usbphynop1 {
 195                 compatible = "usb-nop-xceiv";
 196                 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 197                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 198                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 199                 clock-names = "main_clk";
 200         };
 201
 202         usbphynop2: usbphynop2 {
 203                 compatible = "usb-nop-xceiv";
 204                 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 205                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 206                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 207                 clock-names = "main_clk";
 208         };
 209
 210         soc@0 {
 211                 compatible = "simple-bus";
 212                 #address-cells = <1>;
 213                 #size-cells = <1>;
 214                 ranges = <0x0 0x0 0x0 0x3e000000>;
 215
 216                 aips1: bus@30000000 {
 217                         compatible = "fsl,aips-bus", "simple-bus";
 218                         #address-cells = <1>;
 219                         #size-cells = <1>;
 220                         ranges = <0x30000000 0x30000000 0x400000>;
 221
 222                         sai1: sai@30010000 {
 223                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 224                                 reg = <0x30010000 0x10000>;
 225                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 226                                 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
 227                                          <&clk IMX8MM_CLK_SAI1_ROOT>,
 228                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 229                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 230                                 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
 231                                 dma-names = "rx", "tx";
 232                                 status = "disabled";
 233                         };
 234
 235                         sai2: sai@30020000 {
 236                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 237                                 reg = <0x30020000 0x10000>;
 238                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 239                                 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
 240                                         <&clk IMX8MM_CLK_SAI2_ROOT>,
 241                                         <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 242                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 243                                 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
 244                                 dma-names = "rx", "tx";
 245                                 status = "disabled";
 246                         };
 247
 248                         sai3: sai@30030000 {
 249                                 #sound-dai-cells = <0>;
 250                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 251                                 reg = <0x30030000 0x10000>;
 252                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 253                                 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
 254                                          <&clk IMX8MM_CLK_SAI3_ROOT>,
 255                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 256                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 257                                 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
 258                                 dma-names = "rx", "tx";
 259                                 status = "disabled";
 260                         };
 261
 262                         sai5: sai@30050000 {
 263                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 264                                 reg = <0x30050000 0x10000>;
 265                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 266                                 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
 267                                          <&clk IMX8MM_CLK_SAI5_ROOT>,
 268                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 269                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 270                                 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
 271                                 dma-names = "rx", "tx";
 272                                 status = "disabled";
 273                         };
 274
 275                         sai6: sai@30060000 {
 276                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 277                                 reg = <0x30060000 0x10000>;
 278                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 279                                 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
 280                                          <&clk IMX8MM_CLK_SAI6_ROOT>,
 281                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 282                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 283                                 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
 284                                 dma-names = "rx", "tx";
 285                                 status = "disabled";
 286                         };
 287
 288                         gpio1: gpio@30200000 {
 289                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 290                                 reg = <0x30200000 0x10000>;
 291                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 292                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 293                                 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
 294                                 gpio-controller;
 295                                 #gpio-cells = <2>;
 296                                 interrupt-controller;
 297                                 #interrupt-cells = <2>;
 298                         };
 299
 300                         gpio2: gpio@30210000 {
 301                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 302                                 reg = <0x30210000 0x10000>;
 303                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 304                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 305                                 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
 306                                 gpio-controller;
 307                                 #gpio-cells = <2>;
 308                                 interrupt-controller;
 309                                 #interrupt-cells = <2>;
 310                         };
 311
 312                         gpio3: gpio@30220000 {
 313                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 314                                 reg = <0x30220000 0x10000>;
 315                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 316                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 317                                 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
 318                                 gpio-controller;
 319                                 #gpio-cells = <2>;
 320                                 interrupt-controller;
 321                                 #interrupt-cells = <2>;
 322                         };
 323
 324                         gpio4: gpio@30230000 {
 325                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 326                                 reg = <0x30230000 0x10000>;
 327                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 328                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 329                                 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
 330                                 gpio-controller;
 331                                 #gpio-cells = <2>;
 332                                 interrupt-controller;
 333                                 #interrupt-cells = <2>;
 334                         };
 335
 336                         gpio5: gpio@30240000 {
 337                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 338                                 reg = <0x30240000 0x10000>;
 339                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 340                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 341                                 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
 342                                 gpio-controller;
 343                                 #gpio-cells = <2>;
 344                                 interrupt-controller;
 345                                 #interrupt-cells = <2>;
 346                         };
 347
 348                         wdog1: watchdog@30280000 {
 349                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 350                                 reg = <0x30280000 0x10000>;
 351                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 352                                 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
 353                                 status = "disabled";
 354                         };
 355
 356                         wdog2: watchdog@30290000 {
 357                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 358                                 reg = <0x30290000 0x10000>;
 359                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 360                                 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
 361                                 status = "disabled";
 362                         };
 363
 364                         wdog3: watchdog@302a0000 {
 365                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 366                                 reg = <0x302a0000 0x10000>;
 367                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
 369                                 status = "disabled";
 370                         };
 371
 372                         sdma2: dma-controller@302c0000 {
 373                                 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
 374                                 reg = <0x302c0000 0x10000>;
 375                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
 377                                          <&clk IMX8MM_CLK_SDMA2_ROOT>;
 378                                 clock-names = "ipg", "ahb";
 379                                 #dma-cells = <3>;
 380                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 381                         };
 382
 383                         sdma3: dma-controller@302b0000 {
 384                                 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
 385                                 reg = <0x302b0000 0x10000>;
 386                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 387                                 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
 388                                  <&clk IMX8MM_CLK_SDMA3_ROOT>;
 389                                 clock-names = "ipg", "ahb";
 390                                 #dma-cells = <3>;
 391                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 392                         };
 393
 394                         iomuxc: pinctrl@30330000 {
 395                                 compatible = "fsl,imx8mm-iomuxc";
 396                                 reg = <0x30330000 0x10000>;
 397                         };
 398
 399                         gpr: iomuxc-gpr@30340000 {
 400                                 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
 401                                 reg = <0x30340000 0x10000>;
 402                         };
 403
 404                         ocotp: ocotp-ctrl@30350000 {
 405                                 compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
 406                                 reg = <0x30350000 0x10000>;
 407                                 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
 408                                 /* For nvmem subnodes */
 409                                 #address-cells = <1>;
 410                                 #size-cells = <1>;
 411
 412                                 cpu_speed_grade: speed-grade@10 {
 413                                         reg = <0x10 4>;
 414                                 };
 415                         };
 416
 417                         anatop: anatop@30360000 {
 418                                 compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
 419                                 reg = <0x30360000 0x10000>;
 420                         };
 421
 422                         snvs: snvs@30370000 {
 423                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 424                                 reg = <0x30370000 0x10000>;
 425
 426                                 snvs_rtc: snvs-rtc-lp {
 427                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 428                                         regmap = <&snvs>;
 429                                         offset = <0x34>;
 430                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 431                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 432                                         clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
 433                                         clock-names = "snvs-rtc";
 434                                 };
 435
 436                                 snvs_pwrkey: snvs-powerkey {
 437                                         compatible = "fsl,sec-v4.0-pwrkey";
 438                                         regmap = <&snvs>;
 439                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 440                                         linux,keycode = <KEY_POWER>;
 441                                         wakeup-source;
 442                                         status = "disabled";
 443                                 };
 444                         };
 445
 446                         clk: clock-controller@30380000 {
 447                                 compatible = "fsl,imx8mm-ccm";
 448                                 reg = <0x30380000 0x10000>;
 449                                 #clock-cells = <1>;
 450                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 451                                          <&clk_ext3>, <&clk_ext4>;
 452                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 453                                               "clk_ext3", "clk_ext4";
 454                         };
 455
 456                         src: reset-controller@30390000 {
 457                                 compatible = "fsl,imx8mm-src", "syscon";
 458                                 reg = <0x30390000 0x10000>;
 459                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 460                                 #reset-cells = <1>;
 461                         };
 462                 };
 463
 464                 aips2: bus@30400000 {
 465                         compatible = "fsl,aips-bus", "simple-bus";
 466                         #address-cells = <1>;
 467                         #size-cells = <1>;
 468                         ranges = <0x30400000 0x30400000 0x400000>;
 469
 470                         pwm1: pwm@30660000 {
 471                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 472                                 reg = <0x30660000 0x10000>;
 473                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 474                                 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
 475                                         <&clk IMX8MM_CLK_PWM1_ROOT>;
 476                                 clock-names = "ipg", "per";
 477                                 #pwm-cells = <2>;
 478                                 status = "disabled";
 479                         };
 480
 481                         pwm2: pwm@30670000 {
 482                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 483                                 reg = <0x30670000 0x10000>;
 484                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 485                                 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
 486                                          <&clk IMX8MM_CLK_PWM2_ROOT>;
 487                                 clock-names = "ipg", "per";
 488                                 #pwm-cells = <2>;
 489                                 status = "disabled";
 490                         };
 491
 492                         pwm3: pwm@30680000 {
 493                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 494                                 reg = <0x30680000 0x10000>;
 495                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 496                                 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
 497                                          <&clk IMX8MM_CLK_PWM3_ROOT>;
 498                                 clock-names = "ipg", "per";
 499                                 #pwm-cells = <2>;
 500                                 status = "disabled";
 501                         };
 502
 503                         pwm4: pwm@30690000 {
 504                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 505                                 reg = <0x30690000 0x10000>;
 506                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 507                                 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
 508                                          <&clk IMX8MM_CLK_PWM4_ROOT>;
 509                                 clock-names = "ipg", "per";
 510                                 #pwm-cells = <2>;
 511                                 status = "disabled";
 512                         };
 513                 };
 514
 515                 aips3: bus@30800000 {
 516                         compatible = "fsl,aips-bus", "simple-bus";
 517                         #address-cells = <1>;
 518                         #size-cells = <1>;
 519                         ranges = <0x30800000 0x30800000 0x400000>;
 520
 521                         ecspi1: spi@30820000 {
 522                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 523                                 #address-cells = <1>;
 524                                 #size-cells = <0>;
 525                                 reg = <0x30820000 0x10000>;
 526                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 527                                 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
 528                                          <&clk IMX8MM_CLK_ECSPI1_ROOT>;
 529                                 clock-names = "ipg", "per";
 530                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 531                                 dma-names = "rx", "tx";
 532                                 status = "disabled";
 533                         };
 534
 535                         ecspi2: spi@30830000 {
 536                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 537                                 #address-cells = <1>;
 538                                 #size-cells = <0>;
 539                                 reg = <0x30830000 0x10000>;
 540                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 541                                 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
 542                                          <&clk IMX8MM_CLK_ECSPI2_ROOT>;
 543                                 clock-names = "ipg", "per";
 544                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 545                                 dma-names = "rx", "tx";
 546                                 status = "disabled";
 547                         };
 548
 549                         ecspi3: spi@30840000 {
 550                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 551                                 #address-cells = <1>;
 552                                 #size-cells = <0>;
 553                                 reg = <0x30840000 0x10000>;
 554                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 555                                 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
 556                                          <&clk IMX8MM_CLK_ECSPI3_ROOT>;
 557                                 clock-names = "ipg", "per";
 558                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 559                                 dma-names = "rx", "tx";
 560                                 status = "disabled";
 561                         };
 562
 563                         uart1: serial@30860000 {
 564                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 565                                 reg = <0x30860000 0x10000>;
 566                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 567                                 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
 568                                          <&clk IMX8MM_CLK_UART1_ROOT>;
 569                                 clock-names = "ipg", "per";
 570                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 571                                 dma-names = "rx", "tx";
 572                                 status = "disabled";
 573                         };
 574
 575                         uart3: serial@30880000 {
 576                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 577                                 reg = <0x30880000 0x10000>;
 578                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 579                                 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
 580                                          <&clk IMX8MM_CLK_UART3_ROOT>;
 581                                 clock-names = "ipg", "per";
 582                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 583                                 dma-names = "rx", "tx";
 584                                 status = "disabled";
 585                         };
 586
 587                         uart2: serial@30890000 {
 588                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 589                                 reg = <0x30890000 0x10000>;
 590                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 591                                 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
 592                                          <&clk IMX8MM_CLK_UART2_ROOT>;
 593                                 clock-names = "ipg", "per";
 594                                 status = "disabled";
 595                         };
 596
 597                         i2c1: i2c@30a20000 {
 598                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 599                                 #address-cells = <1>;
 600                                 #size-cells = <0>;
 601                                 reg = <0x30a20000 0x10000>;
 602                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 603                                 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
 604                                 status = "disabled";
 605                         };
 606
 607                         i2c2: i2c@30a30000 {
 608                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 609                                 #address-cells = <1>;
 610                                 #size-cells = <0>;
 611                                 reg = <0x30a30000 0x10000>;
 612                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 613                                 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
 614                                 status = "disabled";
 615                         };
 616
 617                         i2c3: i2c@30a40000 {
 618                                 #address-cells = <1>;
 619                                 #size-cells = <0>;
 620                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 621                                 reg = <0x30a40000 0x10000>;
 622                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 623                                 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
 624                                 status = "disabled";
 625                         };
 626
 627                         i2c4: i2c@30a50000 {
 628                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 629                                 #address-cells = <1>;
 630                                 #size-cells = <0>;
 631                                 reg = <0x30a50000 0x10000>;
 632                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 633                                 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
 634                                 status = "disabled";
 635                         };
 636
 637                         uart4: serial@30a60000 {
 638                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 639                                 reg = <0x30a60000 0x10000>;
 640                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 641                                 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
 642                                          <&clk IMX8MM_CLK_UART4_ROOT>;
 643                                 clock-names = "ipg", "per";
 644                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 645                                 dma-names = "rx", "tx";
 646                                 status = "disabled";
 647                         };
 648
 649                         usdhc1: mmc@30b40000 {
 650                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 651                                 reg = <0x30b40000 0x10000>;
 652                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 653                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 654                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 655                                          <&clk IMX8MM_CLK_USDHC1_ROOT>;
 656                                 clock-names = "ipg", "ahb", "per";
 657                                 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
 658                                 assigned-clock-rates = <400000000>;
 659                                 fsl,tuning-start-tap = <20>;
 660                                 fsl,tuning-step= <2>;
 661                                 bus-width = <4>;
 662                                 status = "disabled";
 663                         };
 664
 665                         usdhc2: mmc@30b50000 {
 666                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 667                                 reg = <0x30b50000 0x10000>;
 668                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 669                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 670                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 671                                          <&clk IMX8MM_CLK_USDHC2_ROOT>;
 672                                 clock-names = "ipg", "ahb", "per";
 673                                 fsl,tuning-start-tap = <20>;
 674                                 fsl,tuning-step= <2>;
 675                                 bus-width = <4>;
 676                                 status = "disabled";
 677                         };
 678
 679                         usdhc3: mmc@30b60000 {
 680                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 681                                 reg = <0x30b60000 0x10000>;
 682                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 683                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 684                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 685                                          <&clk IMX8MM_CLK_USDHC3_ROOT>;
 686                                 clock-names = "ipg", "ahb", "per";
 687                                 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
 688                                 assigned-clock-rates = <400000000>;
 689                                 fsl,tuning-start-tap = <20>;
 690                                 fsl,tuning-step= <2>;
 691                                 bus-width = <4>;
 692                                 status = "disabled";
 693                         };
 694
 695                         sdma1: dma-controller@30bd0000 {
 696                                 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
 697                                 reg = <0x30bd0000 0x10000>;
 698                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 699                                 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
 700                                          <&clk IMX8MM_CLK_SDMA1_ROOT>;
 701                                 clock-names = "ipg", "ahb";
 702                                 #dma-cells = <3>;
 703                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 704                         };
 705
 706                         fec1: ethernet@30be0000 {
 707                                 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
 708                                 reg = <0x30be0000 0x10000>;
 709                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 710                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 711                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 712                                 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
 713                                          <&clk IMX8MM_CLK_ENET1_ROOT>,
 714                                          <&clk IMX8MM_CLK_ENET_TIMER>,
 715                                          <&clk IMX8MM_CLK_ENET_REF>,
 716                                          <&clk IMX8MM_CLK_ENET_PHY_REF>;
 717                                 clock-names = "ipg", "ahb", "ptp",
 718                                               "enet_clk_ref", "enet_out";
 719                                 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
 720                                                   <&clk IMX8MM_CLK_ENET_TIMER>,
 721                                                   <&clk IMX8MM_CLK_ENET_REF>,
 722                                                   <&clk IMX8MM_CLK_ENET_TIMER>;
 723                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
 724                                                          <&clk IMX8MM_SYS_PLL2_100M>,
 725                                                          <&clk IMX8MM_SYS_PLL2_125M>;
 726                                 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
 727                                 fsl,num-tx-queues = <3>;
 728                                 fsl,num-rx-queues = <3>;
 729                                 status = "disabled";
 730                         };
 731
 732                 };
 733
 734                 aips4: bus@32c00000 {
 735                         compatible = "fsl,aips-bus", "simple-bus";
 736                         #address-cells = <1>;
 737                         #size-cells = <1>;
 738                         ranges = <0x32c00000 0x32c00000 0x400000>;
 739
 740                         usbotg1: usb@32e40000 {
 741                                 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 742                                 reg = <0x32e40000 0x200>;
 743                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 744                                 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 745                                 clock-names = "usb1_ctrl_root_clk";
 746                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
 747                                                   <&clk IMX8MM_CLK_USB_CORE_REF>;
 748                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
 749                                                          <&clk IMX8MM_SYS_PLL1_100M>;
 750                                 fsl,usbphy = <&usbphynop1>;
 751                                 fsl,usbmisc = <&usbmisc1 0>;
 752                                 status = "disabled";
 753                         };
 754
 755                         usbmisc1: usbmisc@32e40200 {
 756                                 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
 757                                 #index-cells = <1>;
 758                                 reg = <0x32e40200 0x200>;
 759                         };
 760
 761                         usbotg2: usb@32e50000 {
 762                                 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 763                                 reg = <0x32e50000 0x200>;
 764                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 765                                 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 766                                 clock-names = "usb1_ctrl_root_clk";
 767                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
 768                                                   <&clk IMX8MM_CLK_USB_CORE_REF>;
 769                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
 770                                                          <&clk IMX8MM_SYS_PLL1_100M>;
 771                                 fsl,usbphy = <&usbphynop2>;
 772                                 fsl,usbmisc = <&usbmisc2 0>;
 773                                 status = "disabled";
 774                         };
 775
 776                         usbmisc2: usbmisc@32e50200 {
 777                                 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
 778                                 #index-cells = <1>;
 779                                 reg = <0x32e50200 0x200>;
 780                         };
 781
 782                 };
 783
 784                 dma_apbh: dma-controller@33000000 {
 785                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
 786                         reg = <0x33000000 0x2000>;
 787                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 788                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 789                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 790                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 791                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 792                         #dma-cells = <1>;
 793                         dma-channels = <4>;
 794                         clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
 795                 };
 796
 797                 gpmi: nand-controller@33002000{
 798                         compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
 799                         #address-cells = <1>;
 800                         #size-cells = <1>;
 801                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
 802                         reg-names = "gpmi-nand", "bch";
 803                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 804                         interrupt-names = "bch";
 805                         clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
 806                                  <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
 807                         clock-names = "gpmi_io", "gpmi_bch_apb";
 808                         dmas = <&dma_apbh 0>;
 809                         dma-names = "rx-tx";
 810                         status = "disabled";
 811                 };
 812
 813                 gic: interrupt-controller@38800000 {
 814                         compatible = "arm,gic-v3";
 815                         reg = <0x38800000 0x10000>, /* GIC Dist */
 816                               <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
 817                         #interrupt-cells = <3>;
 818                         interrupt-controller;
 819                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 820                 };
 821         };
 822 };