arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
   8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
   9 #include <dt-bindings/clock/sun8i-de2.h>
  10 #include <dt-bindings/clock/sun8i-tcon-top.h>
  11 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  12 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  13 #include <dt-bindings/reset/sun8i-de2.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "arm,cortex-a53";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         enable-method = "psci";
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         compatible = "arm,cortex-a53";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         reg = <2>;
  42                         enable-method = "psci";
  43                 };
  44
  45                 cpu3: cpu@3 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         reg = <3>;
  49                         enable-method = "psci";
  50                 };
  51         };
  52
  53         de: display-engine {
  54                 compatible = "allwinner,sun50i-h6-display-engine";
  55                 allwinner,pipelines = <&mixer0>;
  56                 status = "disabled";
  57         };
  58
  59         iosc: internal-osc-clk {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <16000000>;
  63                 clock-accuracy = <300000000>;
  64                 clock-output-names = "iosc";
  65         };
  66
  67         osc24M: osc24M_clk {
  68                 #clock-cells = <0>;
  69                 compatible = "fixed-clock";
  70                 clock-frequency = <24000000>;
  71                 clock-output-names = "osc24M";
  72         };
  73
  74         osc32k: osc32k_clk {
  75                 #clock-cells = <0>;
  76                 compatible = "fixed-clock";
  77                 clock-frequency = <32768>;
  78                 clock-output-names = "osc32k";
  79         };
  80
  81         psci {
  82                 compatible = "arm,psci-0.2";
  83                 method = "smc";
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv8-timer";
  88                 interrupts = <GIC_PPI 13
  89                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  90                              <GIC_PPI 14
  91                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  92                              <GIC_PPI 11
  93                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  94                              <GIC_PPI 10
  95                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  96         };
  97
  98         soc {
  99                 compatible = "simple-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 bus@1000000 {
 105                         compatible = "allwinner,sun50i-h6-de3",
 106                                      "allwinner,sun50i-a64-de2";
 107                         reg = <0x1000000 0x400000>;
 108                         allwinner,sram = <&de2_sram 1>;
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111                         ranges = <0 0x1000000 0x400000>;
 112
 113                         display_clocks: clock@0 {
 114                                 compatible = "allwinner,sun50i-h6-de3-clk";
 115                                 reg = <0x0 0x10000>;
 116                                 clocks = <&ccu CLK_DE>,
 117                                          <&ccu CLK_BUS_DE>;
 118                                 clock-names = "mod",
 119                                               "bus";
 120                                 resets = <&ccu RST_BUS_DE>;
 121                                 #clock-cells = <1>;
 122                                 #reset-cells = <1>;
 123                         };
 124
 125                         mixer0: mixer@100000 {
 126                                 compatible = "allwinner,sun50i-h6-de3-mixer-0";
 127                                 reg = <0x100000 0x100000>;
 128                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 129                                          <&display_clocks CLK_MIXER0>;
 130                                 clock-names = "bus",
 131                                               "mod";
 132                                 resets = <&display_clocks RST_MIXER0>;
 133
 134                                 ports {
 135                                         #address-cells = <1>;
 136                                         #size-cells = <0>;
 137
 138                                         mixer0_out: port@1 {
 139                                                 reg = <1>;
 140
 141                                                 mixer0_out_tcon_top_mixer0: endpoint {
 142                                                         remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 143                                                 };
 144                                         };
 145                                 };
 146                         };
 147                 };
 148
 149                 video-codec@1c0e000 {
 150                         compatible = "allwinner,sun50i-h6-video-engine";
 151                         reg = <0x01c0e000 0x2000>;
 152                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 153                                  <&ccu CLK_MBUS_VE>;
 154                         clock-names = "ahb", "mod", "ram";
 155                         resets = <&ccu RST_BUS_VE>;
 156                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 157                         allwinner,sram = <&ve_sram 1>;
 158                 };
 159
 160                 syscon: syscon@3000000 {
 161                         compatible = "allwinner,sun50i-h6-system-control",
 162                                      "allwinner,sun50i-a64-system-control";
 163                         reg = <0x03000000 0x1000>;
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         ranges;
 167
 168                         sram_c: sram@28000 {
 169                                 compatible = "mmio-sram";
 170                                 reg = <0x00028000 0x1e000>;
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173                                 ranges = <0 0x00028000 0x1e000>;
 174
 175                                 de2_sram: sram-section@0 {
 176                                         compatible = "allwinner,sun50i-h6-sram-c",
 177                                                      "allwinner,sun50i-a64-sram-c";
 178                                         reg = <0x0000 0x1e000>;
 179                                 };
 180                         };
 181
 182                         sram_c1: sram@1a00000 {
 183                                 compatible = "mmio-sram";
 184                                 reg = <0x01a00000 0x200000>;
 185                                 #address-cells = <1>;
 186                                 #size-cells = <1>;
 187                                 ranges = <0 0x01a00000 0x200000>;
 188
 189                                 ve_sram: sram-section@0 {
 190                                         compatible = "allwinner,sun50i-h6-sram-c1",
 191                                                      "allwinner,sun4i-a10-sram-c1";
 192                                         reg = <0x000000 0x200000>;
 193                                 };
 194                         };
 195                 };
 196
 197                 ccu: clock@3001000 {
 198                         compatible = "allwinner,sun50i-h6-ccu";
 199                         reg = <0x03001000 0x1000>;
 200                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
 201                         clock-names = "hosc", "losc", "iosc";
 202                         #clock-cells = <1>;
 203                         #reset-cells = <1>;
 204                 };
 205
 206                 dma: dma-controller@3002000 {
 207                         compatible = "allwinner,sun50i-h6-dma";
 208                         reg = <0x03002000 0x1000>;
 209                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 210                         clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
 211                         clock-names = "bus", "mbus";
 212                         dma-channels = <16>;
 213                         dma-requests = <46>;
 214                         resets = <&ccu RST_BUS_DMA>;
 215                         #dma-cells = <1>;
 216                 };
 217
 218                 sid: sid@3006000 {
 219                         compatible = "allwinner,sun50i-h6-sid";
 220                         reg = <0x03006000 0x400>;
 221                 };
 222
 223                 watchdog: watchdog@30090a0 {
 224                         compatible = "allwinner,sun50i-h6-wdt",
 225                                      "allwinner,sun6i-a31-wdt";
 226                         reg = <0x030090a0 0x20>;
 227                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 228                         /* Broken on some H6 boards */
 229                         status = "disabled";
 230                 };
 231
 232                 pio: pinctrl@300b000 {
 233                         compatible = "allwinner,sun50i-h6-pinctrl";
 234                         reg = <0x0300b000 0x400>;
 235                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 239                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
 240                         clock-names = "apb", "hosc", "losc";
 241                         gpio-controller;
 242                         #gpio-cells = <3>;
 243                         interrupt-controller;
 244                         #interrupt-cells = <3>;
 245
 246                         ext_rgmii_pins: rgmii-pins {
 247                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 248                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 249                                        "PD11", "PD12", "PD13", "PD19", "PD20";
 250                                 function = "emac";
 251                                 drive-strength = <40>;
 252                         };
 253
 254                         hdmi_pins: hdmi-pins {
 255                                 pins = "PH8", "PH9", "PH10";
 256                                 function = "hdmi";
 257                         };
 258
 259                         mmc0_pins: mmc0-pins {
 260                                 pins = "PF0", "PF1", "PF2", "PF3",
 261                                        "PF4", "PF5";
 262                                 function = "mmc0";
 263                                 drive-strength = <30>;
 264                                 bias-pull-up;
 265                         };
 266
 267                         /omit-if-no-ref/
 268                         mmc1_pins: mmc1-pins {
 269                                 pins = "PG0", "PG1", "PG2", "PG3",
 270                                        "PG4", "PG5";
 271                                 function = "mmc1";
 272                                 drive-strength = <30>;
 273                                 bias-pull-up;
 274                         };
 275
 276                         mmc2_pins: mmc2-pins {
 277                                 pins = "PC1", "PC4", "PC5", "PC6",
 278                                        "PC7", "PC8", "PC9", "PC10",
 279                                        "PC11", "PC12", "PC13", "PC14";
 280                                 function = "mmc2";
 281                                 drive-strength = <30>;
 282                                 bias-pull-up;
 283                         };
 284
 285                         uart0_ph_pins: uart0-ph-pins {
 286                                 pins = "PH0", "PH1";
 287                                 function = "uart0";
 288                         };
 289                 };
 290
 291                 gic: interrupt-controller@3021000 {
 292                         compatible = "arm,gic-400";
 293                         reg = <0x03021000 0x1000>,
 294                               <0x03022000 0x2000>,
 295                               <0x03024000 0x2000>,
 296                               <0x03026000 0x2000>;
 297                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 298                         interrupt-controller;
 299                         #interrupt-cells = <3>;
 300                 };
 301
 302                 mmc0: mmc@4020000 {
 303                         compatible = "allwinner,sun50i-h6-mmc",
 304                                      "allwinner,sun50i-a64-mmc";
 305                         reg = <0x04020000 0x1000>;
 306                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 307                         clock-names = "ahb", "mmc";
 308                         resets = <&ccu RST_BUS_MMC0>;
 309                         reset-names = "ahb";
 310                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 311                         pinctrl-names = "default";
 312                         pinctrl-0 = <&mmc0_pins>;
 313                         status = "disabled";
 314                         #address-cells = <1>;
 315                         #size-cells = <0>;
 316                 };
 317
 318                 mmc1: mmc@4021000 {
 319                         compatible = "allwinner,sun50i-h6-mmc",
 320                                      "allwinner,sun50i-a64-mmc";
 321                         reg = <0x04021000 0x1000>;
 322                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 323                         clock-names = "ahb", "mmc";
 324                         resets = <&ccu RST_BUS_MMC1>;
 325                         reset-names = "ahb";
 326                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 327                         pinctrl-names = "default";
 328                         pinctrl-0 = <&mmc1_pins>;
 329                         status = "disabled";
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                 };
 333
 334                 mmc2: mmc@4022000 {
 335                         compatible = "allwinner,sun50i-h6-emmc",
 336                                      "allwinner,sun50i-a64-emmc";
 337                         reg = <0x04022000 0x1000>;
 338                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 339                         clock-names = "ahb", "mmc";
 340                         resets = <&ccu RST_BUS_MMC2>;
 341                         reset-names = "ahb";
 342                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 343                         pinctrl-names = "default";
 344                         pinctrl-0 = <&mmc2_pins>;
 345                         status = "disabled";
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                 };
 349
 350                 uart0: serial@5000000 {
 351                         compatible = "snps,dw-apb-uart";
 352                         reg = <0x05000000 0x400>;
 353                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 354                         reg-shift = <2>;
 355                         reg-io-width = <4>;
 356                         clocks = <&ccu CLK_BUS_UART0>;
 357                         resets = <&ccu RST_BUS_UART0>;
 358                         status = "disabled";
 359                 };
 360
 361                 uart1: serial@5000400 {
 362                         compatible = "snps,dw-apb-uart";
 363                         reg = <0x05000400 0x400>;
 364                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 365                         reg-shift = <2>;
 366                         reg-io-width = <4>;
 367                         clocks = <&ccu CLK_BUS_UART1>;
 368                         resets = <&ccu RST_BUS_UART1>;
 369                         status = "disabled";
 370                 };
 371
 372                 uart2: serial@5000800 {
 373                         compatible = "snps,dw-apb-uart";
 374                         reg = <0x05000800 0x400>;
 375                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 376                         reg-shift = <2>;
 377                         reg-io-width = <4>;
 378                         clocks = <&ccu CLK_BUS_UART2>;
 379                         resets = <&ccu RST_BUS_UART2>;
 380                         status = "disabled";
 381                 };
 382
 383                 uart3: serial@5000c00 {
 384                         compatible = "snps,dw-apb-uart";
 385                         reg = <0x05000c00 0x400>;
 386                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 387                         reg-shift = <2>;
 388                         reg-io-width = <4>;
 389                         clocks = <&ccu CLK_BUS_UART3>;
 390                         resets = <&ccu RST_BUS_UART3>;
 391                         status = "disabled";
 392                 };
 393
 394                 emac: ethernet@5020000 {
 395                         compatible = "allwinner,sun50i-h6-emac",
 396                                      "allwinner,sun50i-a64-emac";
 397                         syscon = <&syscon>;
 398                         reg = <0x05020000 0x10000>;
 399                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 400                         interrupt-names = "macirq";
 401                         resets = <&ccu RST_BUS_EMAC>;
 402                         reset-names = "stmmaceth";
 403                         clocks = <&ccu CLK_BUS_EMAC>;
 404                         clock-names = "stmmaceth";
 405                         status = "disabled";
 406
 407                         mdio: mdio {
 408                                 compatible = "snps,dwmac-mdio";
 409                                 #address-cells = <1>;
 410                                 #size-cells = <0>;
 411                         };
 412                 };
 413
 414                 usb2otg: usb@5100000 {
 415                         compatible = "allwinner,sun50i-h6-musb",
 416                                      "allwinner,sun8i-a33-musb";
 417                         reg = <0x05100000 0x0400>;
 418                         clocks = <&ccu CLK_BUS_OTG>;
 419                         resets = <&ccu RST_BUS_OTG>;
 420                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 421                         interrupt-names = "mc";
 422                         phys = <&usb2phy 0>;
 423                         phy-names = "usb";
 424                         extcon = <&usb2phy 0>;
 425                         status = "disabled";
 426                 };
 427
 428                 usb2phy: phy@5100400 {
 429                         compatible = "allwinner,sun50i-h6-usb-phy";
 430                         reg = <0x05100400 0x24>,
 431                               <0x05101800 0x4>,
 432                               <0x05311800 0x4>;
 433                         reg-names = "phy_ctrl",
 434                                     "pmu0",
 435                                     "pmu3";
 436                         clocks = <&ccu CLK_USB_PHY0>,
 437                                  <&ccu CLK_USB_PHY3>;
 438                         clock-names = "usb0_phy",
 439                                       "usb3_phy";
 440                         resets = <&ccu RST_USB_PHY0>,
 441                                  <&ccu RST_USB_PHY3>;
 442                         reset-names = "usb0_reset",
 443                                       "usb3_reset";
 444                         status = "disabled";
 445                         #phy-cells = <1>;
 446                 };
 447
 448                 ehci0: usb@5101000 {
 449                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 450                         reg = <0x05101000 0x100>;
 451                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 452                         clocks = <&ccu CLK_BUS_OHCI0>,
 453                                  <&ccu CLK_BUS_EHCI0>,
 454                                  <&ccu CLK_USB_OHCI0>;
 455                         resets = <&ccu RST_BUS_OHCI0>,
 456                                  <&ccu RST_BUS_EHCI0>;
 457                         status = "disabled";
 458                 };
 459
 460                 ohci0: usb@5101400 {
 461                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 462                         reg = <0x05101400 0x100>;
 463                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&ccu CLK_BUS_OHCI0>,
 465                                  <&ccu CLK_USB_OHCI0>;
 466                         resets = <&ccu RST_BUS_OHCI0>;
 467                         status = "disabled";
 468                 };
 469
 470                 ehci3: usb@5311000 {
 471                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 472                         reg = <0x05311000 0x100>;
 473                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 474                         clocks = <&ccu CLK_BUS_OHCI3>,
 475                                  <&ccu CLK_BUS_EHCI3>,
 476                                  <&ccu CLK_USB_OHCI3>;
 477                         resets = <&ccu RST_BUS_OHCI3>,
 478                                  <&ccu RST_BUS_EHCI3>;
 479                         phys = <&usb2phy 3>;
 480                         status = "disabled";
 481                 };
 482
 483                 ohci3: usb@5311400 {
 484                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 485                         reg = <0x05311400 0x100>;
 486                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 487                         clocks = <&ccu CLK_BUS_OHCI3>,
 488                                  <&ccu CLK_USB_OHCI3>;
 489                         resets = <&ccu RST_BUS_OHCI3>;
 490                         phys = <&usb2phy 3>;
 491                         status = "disabled";
 492                 };
 493
 494                 hdmi: hdmi@6000000 {
 495                         compatible = "allwinner,sun50i-h6-dw-hdmi";
 496                         reg = <0x06000000 0x10000>;
 497                         reg-io-width = <1>;
 498                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 499                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 500                                  <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
 501                                  <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
 502                         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
 503                                       "hdcp-bus";
 504                         resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
 505                         reset-names = "ctrl", "hdcp";
 506                         phys = <&hdmi_phy>;
 507                         phy-names = "hdmi-phy";
 508                         pinctrl-names = "default";
 509                         pinctrl-0 = <&hdmi_pins>;
 510                         status = "disabled";
 511
 512                         ports {
 513                                 #address-cells = <1>;
 514                                 #size-cells = <0>;
 515
 516                                 hdmi_in: port@0 {
 517                                         reg = <0>;
 518
 519                                         hdmi_in_tcon_top: endpoint {
 520                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 521                                         };
 522                                 };
 523
 524                                 hdmi_out: port@1 {
 525                                         reg = <1>;
 526                                 };
 527                         };
 528                 };
 529
 530                 hdmi_phy: hdmi-phy@6010000 {
 531                         compatible = "allwinner,sun50i-h6-hdmi-phy";
 532                         reg = <0x06010000 0x10000>;
 533                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 534                         clock-names = "bus", "mod";
 535                         resets = <&ccu RST_BUS_HDMI>;
 536                         reset-names = "phy";
 537                         #phy-cells = <0>;
 538                 };
 539
 540                 tcon_top: tcon-top@6510000 {
 541                         compatible = "allwinner,sun50i-h6-tcon-top";
 542                         reg = <0x06510000 0x1000>;
 543                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 544                                  <&ccu CLK_TCON_TV0>;
 545                         clock-names = "bus",
 546                                       "tcon-tv0";
 547                         clock-output-names = "tcon-top-tv0";
 548                         resets = <&ccu RST_BUS_TCON_TOP>;
 549                         reset-names = "rst";
 550                         #clock-cells = <1>;
 551
 552                         ports {
 553                                 #address-cells = <1>;
 554                                 #size-cells = <0>;
 555
 556                                 tcon_top_mixer0_in: port@0 {
 557                                         #address-cells = <1>;
 558                                         #size-cells = <0>;
 559                                         reg = <0>;
 560
 561                                         tcon_top_mixer0_in_mixer0: endpoint@0 {
 562                                                 reg = <0>;
 563                                                 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
 564                                         };
 565                                 };
 566
 567                                 tcon_top_mixer0_out: port@1 {
 568                                         #address-cells = <1>;
 569                                         #size-cells = <0>;
 570                                         reg = <1>;
 571
 572                                         tcon_top_mixer0_out_tcon_tv: endpoint@2 {
 573                                                 reg = <2>;
 574                                                 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
 575                                         };
 576                                 };
 577
 578                                 tcon_top_hdmi_in: port@4 {
 579                                         #address-cells = <1>;
 580                                         #size-cells = <0>;
 581                                         reg = <4>;
 582
 583                                         tcon_top_hdmi_in_tcon_tv: endpoint@0 {
 584                                                 reg = <0>;
 585                                                 remote-endpoint = <&tcon_tv_out_tcon_top>;
 586                                         };
 587                                 };
 588
 589                                 tcon_top_hdmi_out: port@5 {
 590                                         reg = <5>;
 591
 592                                         tcon_top_hdmi_out_hdmi: endpoint {
 593                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 594                                         };
 595                                 };
 596                         };
 597                 };
 598
 599                 tcon_tv: lcd-controller@6515000 {
 600                         compatible = "allwinner,sun50i-h6-tcon-tv",
 601                                      "allwinner,sun8i-r40-tcon-tv";
 602                         reg = <0x06515000 0x1000>;
 603                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 604                         clocks = <&ccu CLK_BUS_TCON_TV0>,
 605                                  <&tcon_top CLK_TCON_TOP_TV0>;
 606                         clock-names = "ahb",
 607                                       "tcon-ch1";
 608                         resets = <&ccu RST_BUS_TCON_TV0>;
 609                         reset-names = "lcd";
 610
 611                         ports {
 612                                 #address-cells = <1>;
 613                                 #size-cells = <0>;
 614
 615                                 tcon_tv_in: port@0 {
 616                                         reg = <0>;
 617
 618                                         tcon_tv_in_tcon_top_mixer0: endpoint {
 619                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
 620                                         };
 621                                 };
 622
 623                                 tcon_tv_out: port@1 {
 624                                         #address-cells = <1>;
 625                                         #size-cells = <0>;
 626                                         reg = <1>;
 627
 628                                         tcon_tv_out_tcon_top: endpoint@1 {
 629                                                 reg = <1>;
 630                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
 631                                         };
 632                                 };
 633                         };
 634                 };
 635
 636                 r_ccu: clock@7010000 {
 637                         compatible = "allwinner,sun50i-h6-r-ccu";
 638                         reg = <0x07010000 0x400>;
 639                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 640                                  <&ccu CLK_PLL_PERIPH0>;
 641                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 642                         #clock-cells = <1>;
 643                         #reset-cells = <1>;
 644                 };
 645
 646                 r_watchdog: watchdog@7020400 {
 647                         compatible = "allwinner,sun50i-h6-wdt",
 648                                      "allwinner,sun6i-a31-wdt";
 649                         reg = <0x07020400 0x20>;
 650                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 651                 };
 652
 653                 r_intc: interrupt-controller@7021000 {
 654                         compatible = "allwinner,sun50i-h6-r-intc",
 655                                      "allwinner,sun6i-a31-r-intc";
 656                         interrupt-controller;
 657                         #interrupt-cells = <2>;
 658                         reg = <0x07021000 0x400>;
 659                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 660                 };
 661
 662                 r_pio: pinctrl@7022000 {
 663                         compatible = "allwinner,sun50i-h6-r-pinctrl";
 664                         reg = <0x07022000 0x400>;
 665                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 666                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 667                         clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
 668                         clock-names = "apb", "hosc", "losc";
 669                         gpio-controller;
 670                         #gpio-cells = <3>;
 671                         interrupt-controller;
 672                         #interrupt-cells = <3>;
 673
 674                         r_i2c_pins: r-i2c-pins {
 675                                 pins = "PL0", "PL1";
 676                                 function = "s_i2c";
 677                         };
 678                 };
 679
 680                 r_i2c: i2c@7081400 {
 681                         compatible = "allwinner,sun6i-a31-i2c";
 682                         reg = <0x07081400 0x400>;
 683                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 684                         clocks = <&r_ccu CLK_R_APB2_I2C>;
 685                         resets = <&r_ccu RST_R_APB2_I2C>;
 686                         pinctrl-names = "default";
 687                         pinctrl-0 = <&r_i2c_pins>;
 688                         status = "disabled";
 689                         #address-cells = <1>;
 690                         #size-cells = <0>;
 691                 };
 692         };
 693 };