3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 DECLARE_GLOBAL_DATA_PTR;
22 struct sdram_addr_dec {
23 struct sdram_bank sdram_bank[4];
26 #define REG_CPUCS_WIN_ENABLE (1 << 0)
27 #define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
28 #define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
29 #define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
32 * mvebu_sdram_bar - reads SDRAM Base Address Register
34 u32 mvebu_sdram_bar(enum memory_bank bank)
36 struct sdram_addr_dec *base =
37 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
39 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
41 if ((!enable) || (bank > BANK3))
44 result = readl(&base->sdram_bank[bank].win_bar);
49 * mvebu_sdram_bs_set - writes SDRAM Bank size
51 static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
53 struct sdram_addr_dec *base =
54 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
55 /* Read current register value */
56 u32 reg = readl(&base->sdram_bank[bank].win_sz);
58 /* Clear window size */
59 reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
61 /* Set new window size */
62 reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
64 writel(reg, &base->sdram_bank[bank].win_sz);
68 * mvebu_sdram_bs - reads SDRAM Bank size
70 u32 mvebu_sdram_bs(enum memory_bank bank)
72 struct sdram_addr_dec *base =
73 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
75 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
77 if ((!enable) || (bank > BANK3))
79 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
84 void mvebu_sdram_size_adjust(enum memory_bank bank)
88 /* probe currently equipped RAM size */
89 size = get_ram_size((void *)mvebu_sdram_bar(bank),
90 mvebu_sdram_bs(bank));
92 /* adjust SDRAM window size accordingly */
93 mvebu_sdram_bs_set(bank, size);
96 #ifndef CONFIG_SYS_BOARD_DRAM_INIT
102 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
103 gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
104 gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
106 * It is assumed that all memory banks are consecutive
108 * If the gap is found, ram_size will be reported for
109 * consecutive memory only
111 if (gd->bd->bi_dram[i].start != gd->ram_size)
115 * Don't report more than 3GiB of SDRAM, otherwise there is no
116 * address space left for the internal registers etc.
118 if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) &&
119 (gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30)))
120 gd->ram_size += gd->bd->bi_dram[i].size;
124 for (; i < CONFIG_NR_DRAM_BANKS; i++) {
125 /* If above loop terminated prematurely, we need to set
126 * remaining banks' start address & size as 0. Otherwise other
127 * u-boot functions and Linux kernel gets wrong values which
128 * could result in crash */
129 gd->bd->bi_dram[i].start = 0;
130 gd->bd->bi_dram[i].size = 0;
137 * If this function is not defined here,
138 * board.c alters dram bank zero configuration defined above.
140 void dram_init_banksize(void)
144 #endif /* CONFIG_SYS_BOARD_DRAM_INIT */