arch/arm/mach-zynqmp/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <time.h>
   9 #include <asm/arch/hardware.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/armv8/mmu.h>
  12 #include <asm/cache.h>
  13 #include <asm/io.h>
  14 #include <zynqmp_firmware.h>
  15 #include <asm/cache.h>
  16
  17 #define ZYNQ_SILICON_VER_MASK   0xF000
  18 #define ZYNQ_SILICON_VER_SHIFT  12
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /*
  23  * Number of filled static entries and also the first empty
  24  * slot in zynqmp_mem_map.
  25  */
  26 #define ZYNQMP_MEM_MAP_USED     4
  27
  28 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  29 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  30 #else
  31 #define DRAM_BANKS 0
  32 #endif
  33
  34 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  35 #define TCM_MAP 1
  36 #else
  37 #define TCM_MAP 0
  38 #endif
  39
  40 /* +1 is end of list which needs to be empty */
  41 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  42
  43 static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
  44         {
  45                 .virt = 0x80000000UL,
  46                 .phys = 0x80000000UL,
  47                 .size = 0x70000000UL,
  48                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  49                          PTE_BLOCK_NON_SHARE |
  50                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  51         }, {
  52                 .virt = 0xf8000000UL,
  53                 .phys = 0xf8000000UL,
  54                 .size = 0x07e00000UL,
  55                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56                          PTE_BLOCK_NON_SHARE |
  57                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  58         }, {
  59                 .virt = 0x400000000UL,
  60                 .phys = 0x400000000UL,
  61                 .size = 0x400000000UL,
  62                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  63                          PTE_BLOCK_NON_SHARE |
  64                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  65         }, {
  66                 .virt = 0x1000000000UL,
  67                 .phys = 0x1000000000UL,
  68                 .size = 0xf000000000UL,
  69                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  70                          PTE_BLOCK_NON_SHARE |
  71                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  72         }
  73 };
  74
  75 void mem_map_fill(void)
  76 {
  77         int banks = ZYNQMP_MEM_MAP_USED;
  78
  79 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  80         zynqmp_mem_map[banks].virt = 0xffe00000UL;
  81         zynqmp_mem_map[banks].phys = 0xffe00000UL;
  82         zynqmp_mem_map[banks].size = 0x00200000UL;
  83         zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  84                                       PTE_BLOCK_INNER_SHARE;
  85         banks = banks + 1;
  86 #endif
  87
  88 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  89         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  90                 /* Zero size means no more DDR that's this is end */
  91                 if (!gd->bd->bi_dram[i].size)
  92                         break;
  93
  94                 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  95                 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  96                 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
  97                 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  98                                               PTE_BLOCK_INNER_SHARE;
  99                 banks = banks + 1;
 100         }
 101 #endif
 102 }
 103
 104 struct mm_region *mem_map = zynqmp_mem_map;
 105
 106 u64 get_page_table_size(void)
 107 {
 108         return 0x14000;
 109 }
 110
 111 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
 112 void tcm_init(u8 mode)
 113 {
 114         puts("WARNING: Initializing TCM overwrites TCM content\n");
 115         initialize_tcm(mode);
 116         memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
 117 }
 118 #endif
 119
 120 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
 121 int arm_reserve_mmu(void)
 122 {
 123         tcm_init(TCM_LOCK);
 124         gd->arch.tlb_size = PGTABLE_SIZE;
 125         gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
 126
 127         return 0;
 128 }
 129 #endif
 130
 131 static unsigned int zynqmp_get_silicon_version_secure(void)
 132 {
 133         u32 ver;
 134
 135         ver = readl(&csu_base->version);
 136         ver &= ZYNQMP_SILICON_VER_MASK;
 137         ver >>= ZYNQMP_SILICON_VER_SHIFT;
 138
 139         return ver;
 140 }
 141
 142 unsigned int zynqmp_get_silicon_version(void)
 143 {
 144         if (current_el() == 3)
 145                 return zynqmp_get_silicon_version_secure();
 146
 147         gd->cpu_clk = get_tbclk();
 148
 149         switch (gd->cpu_clk) {
 150         case 50000000:
 151                 return ZYNQMP_CSU_VERSION_QEMU;
 152         }
 153
 154         return ZYNQMP_CSU_VERSION_SILICON;
 155 }
 156
 157 static int zynqmp_mmio_rawwrite(const u32 address,
 158                       const u32 mask,
 159                       const u32 value)
 160 {
 161         u32 data;
 162         u32 value_local = value;
 163         int ret;
 164
 165         ret = zynqmp_mmio_read(address, &data);
 166         if (ret)
 167                 return ret;
 168
 169         data &= ~mask;
 170         value_local &= mask;
 171         value_local |= data;
 172         writel(value_local, (ulong)address);
 173         return 0;
 174 }
 175
 176 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
 177 {
 178         *value = readl((ulong)address);
 179         return 0;
 180 }
 181
 182 int zynqmp_mmio_write(const u32 address,
 183                       const u32 mask,
 184                       const u32 value)
 185 {
 186         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
 187                 return zynqmp_mmio_rawwrite(address, mask, value);
 188 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 189         else
 190                 return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
 191                                          value, 0, NULL);
 192 #endif
 193
 194         return -EINVAL;
 195 }
 196
 197 int zynqmp_mmio_read(const u32 address, u32 *value)
 198 {
 199         u32 ret = -EINVAL;
 200
 201         if (!value)
 202                 return ret;
 203
 204         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 205                 ret = zynqmp_mmio_rawread(address, value);
 206         }
 207 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 208         else {
 209                 u32 ret_payload[PAYLOAD_ARG_CNT];
 210
 211                 ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
 212                                         0, ret_payload);
 213                 *value = ret_payload[1];
 214         }
 215 #endif
 216
 217         return ret;
 218 }