arch/arm/mach-zynqmp/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <time.h>
   9 #include <asm/arch/hardware.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/armv8/mmu.h>
  12 #include <asm/io.h>
  13 #include <zynqmp_firmware.h>
  14 #include <asm/cache.h>
  15
  16 #define ZYNQ_SILICON_VER_MASK   0xF000
  17 #define ZYNQ_SILICON_VER_SHIFT  12
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 /*
  22  * Number of filled static entries and also the first empty
  23  * slot in zynqmp_mem_map.
  24  */
  25 #define ZYNQMP_MEM_MAP_USED     4
  26
  27 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  28 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  29 #else
  30 #define DRAM_BANKS 0
  31 #endif
  32
  33 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  34 #define TCM_MAP 1
  35 #else
  36 #define TCM_MAP 0
  37 #endif
  38
  39 /* +1 is end of list which needs to be empty */
  40 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  41
  42 static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
  43         {
  44                 .virt = 0x80000000UL,
  45                 .phys = 0x80000000UL,
  46                 .size = 0x70000000UL,
  47                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  48                          PTE_BLOCK_NON_SHARE |
  49                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  50         }, {
  51                 .virt = 0xf8000000UL,
  52                 .phys = 0xf8000000UL,
  53                 .size = 0x07e00000UL,
  54                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  55                          PTE_BLOCK_NON_SHARE |
  56                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  57         }, {
  58                 .virt = 0x400000000UL,
  59                 .phys = 0x400000000UL,
  60                 .size = 0x400000000UL,
  61                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  62                          PTE_BLOCK_NON_SHARE |
  63                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  64         }, {
  65                 .virt = 0x1000000000UL,
  66                 .phys = 0x1000000000UL,
  67                 .size = 0xf000000000UL,
  68                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  69                          PTE_BLOCK_NON_SHARE |
  70                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  71         }
  72 };
  73
  74 void mem_map_fill(void)
  75 {
  76         int banks = ZYNQMP_MEM_MAP_USED;
  77
  78 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  79         zynqmp_mem_map[banks].virt = 0xffe00000UL;
  80         zynqmp_mem_map[banks].phys = 0xffe00000UL;
  81         zynqmp_mem_map[banks].size = 0x00200000UL;
  82         zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  83                                       PTE_BLOCK_INNER_SHARE;
  84         banks = banks + 1;
  85 #endif
  86
  87 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  88         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  89                 /* Zero size means no more DDR that's this is end */
  90                 if (!gd->bd->bi_dram[i].size)
  91                         break;
  92
  93                 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  94                 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  95                 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
  96                 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  97                                               PTE_BLOCK_INNER_SHARE;
  98                 banks = banks + 1;
  99         }
 100 #endif
 101 }
 102
 103 struct mm_region *mem_map = zynqmp_mem_map;
 104
 105 u64 get_page_table_size(void)
 106 {
 107         return 0x14000;
 108 }
 109
 110 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
 111 void tcm_init(u8 mode)
 112 {
 113         puts("WARNING: Initializing TCM overwrites TCM content\n");
 114         initialize_tcm(mode);
 115         memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
 116 }
 117 #endif
 118
 119 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
 120 int arm_reserve_mmu(void)
 121 {
 122         tcm_init(TCM_LOCK);
 123         gd->arch.tlb_size = PGTABLE_SIZE;
 124         gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
 125
 126         return 0;
 127 }
 128 #endif
 129
 130 static unsigned int zynqmp_get_silicon_version_secure(void)
 131 {
 132         u32 ver;
 133
 134         ver = readl(&csu_base->version);
 135         ver &= ZYNQMP_SILICON_VER_MASK;
 136         ver >>= ZYNQMP_SILICON_VER_SHIFT;
 137
 138         return ver;
 139 }
 140
 141 unsigned int zynqmp_get_silicon_version(void)
 142 {
 143         if (current_el() == 3)
 144                 return zynqmp_get_silicon_version_secure();
 145
 146         gd->cpu_clk = get_tbclk();
 147
 148         switch (gd->cpu_clk) {
 149         case 50000000:
 150                 return ZYNQMP_CSU_VERSION_QEMU;
 151         }
 152
 153         return ZYNQMP_CSU_VERSION_SILICON;
 154 }
 155
 156 static int zynqmp_mmio_rawwrite(const u32 address,
 157                       const u32 mask,
 158                       const u32 value)
 159 {
 160         u32 data;
 161         u32 value_local = value;
 162         int ret;
 163
 164         ret = zynqmp_mmio_read(address, &data);
 165         if (ret)
 166                 return ret;
 167
 168         data &= ~mask;
 169         value_local &= mask;
 170         value_local |= data;
 171         writel(value_local, (ulong)address);
 172         return 0;
 173 }
 174
 175 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
 176 {
 177         *value = readl((ulong)address);
 178         return 0;
 179 }
 180
 181 int zynqmp_mmio_write(const u32 address,
 182                       const u32 mask,
 183                       const u32 value)
 184 {
 185         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
 186                 return zynqmp_mmio_rawwrite(address, mask, value);
 187 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 188         else
 189                 return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
 190                                          value, 0, NULL);
 191 #endif
 192
 193         return -EINVAL;
 194 }
 195
 196 int zynqmp_mmio_read(const u32 address, u32 *value)
 197 {
 198         u32 ret = -EINVAL;
 199
 200         if (!value)
 201                 return ret;
 202
 203         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 204                 ret = zynqmp_mmio_rawread(address, value);
 205         }
 206 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 207         else {
 208                 u32 ret_payload[PAYLOAD_ARG_CNT];
 209
 210                 ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
 211                                         0, ret_payload);
 212                 *value = ret_payload[1];
 213         }
 214 #endif
 215
 216         return ret;
 217 }