1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
8 #include <asm/arch/hardware.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/armv8/mmu.h>
13 #define ZYNQ_SILICON_VER_MASK 0xF000
14 #define ZYNQ_SILICON_VER_SHIFT 12
16 DECLARE_GLOBAL_DATA_PTR;
19 * Number of filled static entries and also the first empty
20 * slot in zynqmp_mem_map.
22 #define ZYNQMP_MEM_MAP_USED 4
24 #if !defined(CONFIG_ZYNQMP_NO_DDR)
25 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
30 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
36 /* +1 is end of list which needs to be empty */
37 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
39 static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_PXN | PTE_BLOCK_UXN
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
53 PTE_BLOCK_PXN | PTE_BLOCK_UXN
55 .virt = 0x400000000UL,
56 .phys = 0x400000000UL,
57 .size = 0x400000000UL,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
60 PTE_BLOCK_PXN | PTE_BLOCK_UXN
62 .virt = 0x1000000000UL,
63 .phys = 0x1000000000UL,
64 .size = 0xf000000000UL,
65 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
67 PTE_BLOCK_PXN | PTE_BLOCK_UXN
71 void mem_map_fill(void)
73 int banks = ZYNQMP_MEM_MAP_USED;
75 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
76 zynqmp_mem_map[banks].virt = 0xffe00000UL;
77 zynqmp_mem_map[banks].phys = 0xffe00000UL;
78 zynqmp_mem_map[banks].size = 0x00200000UL;
79 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
80 PTE_BLOCK_INNER_SHARE;
84 #if !defined(CONFIG_ZYNQMP_NO_DDR)
85 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
86 /* Zero size means no more DDR that's this is end */
87 if (!gd->bd->bi_dram[i].size)
90 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
91 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
92 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
93 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
94 PTE_BLOCK_INNER_SHARE;
100 struct mm_region *mem_map = zynqmp_mem_map;
102 u64 get_page_table_size(void)
107 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
108 void tcm_init(u8 mode)
110 puts("WARNING: Initializing TCM overwrites TCM content\n");
111 initialize_tcm(mode);
112 memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
116 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
117 int reserve_mmu(void)
120 gd->arch.tlb_size = PGTABLE_SIZE;
121 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
127 static unsigned int zynqmp_get_silicon_version_secure(void)
131 ver = readl(&csu_base->version);
132 ver &= ZYNQMP_SILICON_VER_MASK;
133 ver >>= ZYNQMP_SILICON_VER_SHIFT;
138 unsigned int zynqmp_get_silicon_version(void)
140 if (current_el() == 3)
141 return zynqmp_get_silicon_version_secure();
143 gd->cpu_clk = get_tbclk();
145 switch (gd->cpu_clk) {
147 return ZYNQMP_CSU_VERSION_QEMU;
150 return ZYNQMP_CSU_VERSION_SILICON;
153 #define ZYNQMP_MMIO_READ 0xC2000014
154 #define ZYNQMP_MMIO_WRITE 0xC2000013
156 int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
157 u32 arg3, u32 *ret_payload)
160 * Added SIP service call Function Identifier
161 * Make sure to stay in x0 register
165 regs.regs[0] = pm_api_id;
166 regs.regs[1] = ((u64)arg1 << 32) | arg0;
167 regs.regs[2] = ((u64)arg3 << 32) | arg2;
171 if (ret_payload != NULL) {
172 ret_payload[0] = (u32)regs.regs[0];
173 ret_payload[1] = upper_32_bits(regs.regs[0]);
174 ret_payload[2] = (u32)regs.regs[1];
175 ret_payload[3] = upper_32_bits(regs.regs[1]);
176 ret_payload[4] = (u32)regs.regs[2];
182 unsigned int __maybe_unused zynqmp_pmufw_version(void)
185 u32 ret_payload[PAYLOAD_ARG_CNT];
186 static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID;
189 * Get PMU version only once and later
190 * just return stored values instead of
191 * asking PMUFW again.
193 if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
194 ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
196 pm_api_version = ret_payload[1];
199 panic("PMUFW is not found - Please load it!\n");
202 return pm_api_version;
205 static int zynqmp_mmio_rawwrite(const u32 address,
210 u32 value_local = value;
213 ret = zynqmp_mmio_read(address, &data);
220 writel(value_local, (ulong)address);
224 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
226 *value = readl((ulong)address);
230 int zynqmp_mmio_write(const u32 address,
234 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
235 return zynqmp_mmio_rawwrite(address, mask, value);
237 return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
243 int zynqmp_mmio_read(const u32 address, u32 *value)
245 u32 ret_payload[PAYLOAD_ARG_CNT];
251 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
252 ret = zynqmp_mmio_rawread(address, value);
254 ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
256 *value = ret_payload[1];