arch/arm/mach-zynqmp/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <time.h>
   9 #include <asm/arch/hardware.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/armv8/mmu.h>
  12 #include <asm/io.h>
  13 #include <zynqmp_firmware.h>
  14
  15 #define ZYNQ_SILICON_VER_MASK   0xF000
  16 #define ZYNQ_SILICON_VER_SHIFT  12
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /*
  21  * Number of filled static entries and also the first empty
  22  * slot in zynqmp_mem_map.
  23  */
  24 #define ZYNQMP_MEM_MAP_USED     4
  25
  26 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  27 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  28 #else
  29 #define DRAM_BANKS 0
  30 #endif
  31
  32 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  33 #define TCM_MAP 1
  34 #else
  35 #define TCM_MAP 0
  36 #endif
  37
  38 /* +1 is end of list which needs to be empty */
  39 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  40
  41 static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
  42         {
  43                 .virt = 0x80000000UL,
  44                 .phys = 0x80000000UL,
  45                 .size = 0x70000000UL,
  46                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  47                          PTE_BLOCK_NON_SHARE |
  48                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  49         }, {
  50                 .virt = 0xf8000000UL,
  51                 .phys = 0xf8000000UL,
  52                 .size = 0x07e00000UL,
  53                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  54                          PTE_BLOCK_NON_SHARE |
  55                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  56         }, {
  57                 .virt = 0x400000000UL,
  58                 .phys = 0x400000000UL,
  59                 .size = 0x400000000UL,
  60                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  61                          PTE_BLOCK_NON_SHARE |
  62                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  63         }, {
  64                 .virt = 0x1000000000UL,
  65                 .phys = 0x1000000000UL,
  66                 .size = 0xf000000000UL,
  67                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  68                          PTE_BLOCK_NON_SHARE |
  69                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  70         }
  71 };
  72
  73 void mem_map_fill(void)
  74 {
  75         int banks = ZYNQMP_MEM_MAP_USED;
  76
  77 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  78         zynqmp_mem_map[banks].virt = 0xffe00000UL;
  79         zynqmp_mem_map[banks].phys = 0xffe00000UL;
  80         zynqmp_mem_map[banks].size = 0x00200000UL;
  81         zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  82                                       PTE_BLOCK_INNER_SHARE;
  83         banks = banks + 1;
  84 #endif
  85
  86 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  87         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  88                 /* Zero size means no more DDR that's this is end */
  89                 if (!gd->bd->bi_dram[i].size)
  90                         break;
  91
  92                 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  93                 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  94                 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
  95                 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  96                                               PTE_BLOCK_INNER_SHARE;
  97                 banks = banks + 1;
  98         }
  99 #endif
 100 }
 101
 102 struct mm_region *mem_map = zynqmp_mem_map;
 103
 104 u64 get_page_table_size(void)
 105 {
 106         return 0x14000;
 107 }
 108
 109 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
 110 void tcm_init(u8 mode)
 111 {
 112         puts("WARNING: Initializing TCM overwrites TCM content\n");
 113         initialize_tcm(mode);
 114         memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
 115 }
 116 #endif
 117
 118 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
 119 int reserve_mmu(void)
 120 {
 121         tcm_init(TCM_LOCK);
 122         gd->arch.tlb_size = PGTABLE_SIZE;
 123         gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
 124
 125         return 0;
 126 }
 127 #endif
 128
 129 static unsigned int zynqmp_get_silicon_version_secure(void)
 130 {
 131         u32 ver;
 132
 133         ver = readl(&csu_base->version);
 134         ver &= ZYNQMP_SILICON_VER_MASK;
 135         ver >>= ZYNQMP_SILICON_VER_SHIFT;
 136
 137         return ver;
 138 }
 139
 140 unsigned int zynqmp_get_silicon_version(void)
 141 {
 142         if (current_el() == 3)
 143                 return zynqmp_get_silicon_version_secure();
 144
 145         gd->cpu_clk = get_tbclk();
 146
 147         switch (gd->cpu_clk) {
 148         case 50000000:
 149                 return ZYNQMP_CSU_VERSION_QEMU;
 150         }
 151
 152         return ZYNQMP_CSU_VERSION_SILICON;
 153 }
 154
 155 static int zynqmp_mmio_rawwrite(const u32 address,
 156                       const u32 mask,
 157                       const u32 value)
 158 {
 159         u32 data;
 160         u32 value_local = value;
 161         int ret;
 162
 163         ret = zynqmp_mmio_read(address, &data);
 164         if (ret)
 165                 return ret;
 166
 167         data &= ~mask;
 168         value_local &= mask;
 169         value_local |= data;
 170         writel(value_local, (ulong)address);
 171         return 0;
 172 }
 173
 174 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
 175 {
 176         *value = readl((ulong)address);
 177         return 0;
 178 }
 179
 180 int zynqmp_mmio_write(const u32 address,
 181                       const u32 mask,
 182                       const u32 value)
 183 {
 184         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
 185                 return zynqmp_mmio_rawwrite(address, mask, value);
 186 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 187         else
 188                 return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
 189                                          value, 0, NULL);
 190 #endif
 191
 192         return -EINVAL;
 193 }
 194
 195 int zynqmp_mmio_read(const u32 address, u32 *value)
 196 {
 197         u32 ret = -EINVAL;
 198
 199         if (!value)
 200                 return ret;
 201
 202         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 203                 ret = zynqmp_mmio_rawread(address, value);
 204         }
 205 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 206         else {
 207                 u32 ret_payload[PAYLOAD_ARG_CNT];
 208
 209                 ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
 210                                         0, ret_payload);
 211                 *value = ret_payload[1];
 212         }
 213 #endif
 214
 215         return ret;
 216 }