1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
9 #include <asm/arch/hardware.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/armv8/mmu.h>
13 #include <zynqmp_firmware.h>
15 #define ZYNQ_SILICON_VER_MASK 0xF000
16 #define ZYNQ_SILICON_VER_SHIFT 12
18 DECLARE_GLOBAL_DATA_PTR;
21 * Number of filled static entries and also the first empty
22 * slot in zynqmp_mem_map.
24 #define ZYNQMP_MEM_MAP_USED 4
26 #if !defined(CONFIG_ZYNQMP_NO_DDR)
27 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
32 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
38 /* +1 is end of list which needs to be empty */
39 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
41 static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
46 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
48 PTE_BLOCK_PXN | PTE_BLOCK_UXN
53 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
55 PTE_BLOCK_PXN | PTE_BLOCK_UXN
57 .virt = 0x400000000UL,
58 .phys = 0x400000000UL,
59 .size = 0x400000000UL,
60 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
62 PTE_BLOCK_PXN | PTE_BLOCK_UXN
64 .virt = 0x1000000000UL,
65 .phys = 0x1000000000UL,
66 .size = 0xf000000000UL,
67 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
69 PTE_BLOCK_PXN | PTE_BLOCK_UXN
73 void mem_map_fill(void)
75 int banks = ZYNQMP_MEM_MAP_USED;
77 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
78 zynqmp_mem_map[banks].virt = 0xffe00000UL;
79 zynqmp_mem_map[banks].phys = 0xffe00000UL;
80 zynqmp_mem_map[banks].size = 0x00200000UL;
81 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
82 PTE_BLOCK_INNER_SHARE;
86 #if !defined(CONFIG_ZYNQMP_NO_DDR)
87 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
88 /* Zero size means no more DDR that's this is end */
89 if (!gd->bd->bi_dram[i].size)
92 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
93 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
94 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
95 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
96 PTE_BLOCK_INNER_SHARE;
102 struct mm_region *mem_map = zynqmp_mem_map;
104 u64 get_page_table_size(void)
109 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
110 void tcm_init(u8 mode)
112 puts("WARNING: Initializing TCM overwrites TCM content\n");
113 initialize_tcm(mode);
114 memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
118 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
119 int reserve_mmu(void)
122 gd->arch.tlb_size = PGTABLE_SIZE;
123 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
129 static unsigned int zynqmp_get_silicon_version_secure(void)
133 ver = readl(&csu_base->version);
134 ver &= ZYNQMP_SILICON_VER_MASK;
135 ver >>= ZYNQMP_SILICON_VER_SHIFT;
140 unsigned int zynqmp_get_silicon_version(void)
142 if (current_el() == 3)
143 return zynqmp_get_silicon_version_secure();
145 gd->cpu_clk = get_tbclk();
147 switch (gd->cpu_clk) {
149 return ZYNQMP_CSU_VERSION_QEMU;
152 return ZYNQMP_CSU_VERSION_SILICON;
155 static int zynqmp_mmio_rawwrite(const u32 address,
160 u32 value_local = value;
163 ret = zynqmp_mmio_read(address, &data);
170 writel(value_local, (ulong)address);
174 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
176 *value = readl((ulong)address);
180 int zynqmp_mmio_write(const u32 address,
184 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
185 return zynqmp_mmio_rawwrite(address, mask, value);
186 #if defined(CONFIG_ZYNQMP_FIRMWARE)
188 return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
195 int zynqmp_mmio_read(const u32 address, u32 *value)
202 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
203 ret = zynqmp_mmio_rawread(address, value);
205 #if defined(CONFIG_ZYNQMP_FIRMWARE)
207 u32 ret_payload[PAYLOAD_ARG_CNT];
209 ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
211 *value = ret_payload[1];