2 * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
3 * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
5 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
6 * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved.
9 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
12 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
14 * (C) Copyright 2002-2004
15 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
18 * Texas Instruments <www.ti.com>
21 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
22 * Marius Groeger <mgroeger@sysgo.de>
25 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
26 * Alex Zuepke <azu@sysgo.de>
28 * SPDX-License-Identifier: GPL-2.0+
36 #include <asm/arch/hardware.h>
37 #include <asm/arch/clk.h>
39 DECLARE_GLOBAL_DATA_PTR;
42 u32 load; /* Timer Load Register */
43 u32 counter; /* Timer Counter Register */
44 u32 control; /* Timer Control Register */
47 static struct scu_timer *timer_base =
48 (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR;
50 #define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
51 #define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
52 #define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */
53 #define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */
55 #define TIMER_LOAD_VAL 0xFFFFFFFF
56 #define TIMER_PRESCALE 255
60 const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
61 (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
62 SCUTIMER_CONTROL_ENABLE_MASK;
68 ret = uclass_get_device_by_driver(UCLASS_CLK,
69 DM_GET_DRIVER(zynq_clk), &dev);
73 clk.id = cpu_6or4x_clk;
74 ret = clk_request(dev, &clk);
78 gd->cpu_clk = clk_get_rate(&clk);
82 gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
84 /* Load the timer counter register */
85 writel(0xFFFFFFFF, &timer_base->load);
88 * Start the A9Timer device
89 * Enable Auto reload mode, Clear prescaler control bits
90 * Set prescaler value, Enable the decrementer
92 clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
96 gd->arch.lastinc = readl(&timer_base->counter) /
97 (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
104 * This function is derived from PowerPC code (timebase clock frequency).
105 * On ARM it returns the number of timer ticks per second.
107 ulong get_tbclk(void)
109 return gd->arch.timer_rate_hz;