2 * Copyright (c) 2013 Xilinx Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/clk.h>
14 #define SLCR_LOCK_MAGIC 0x767B
15 #define SLCR_UNLOCK_MAGIC 0xDF0D
17 #define SLCR_USB_L1_SEL 0x04
19 #define SLCR_IDCODE_MASK 0x1F000
20 #define SLCR_IDCODE_SHIFT 12
23 * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
25 * @peri_name: Name of the peripheral for checking MIO status
26 * @get_pins: Pointer to array of get pin for this peripheral
27 * @num_pins: Number of pins for this peripheral
29 * @check_val: Required check value to get the status of periph
31 struct zynq_slcr_mio_get_status {
32 const char *peri_name;
39 static const int usb0_pins[] = {
40 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
43 static const int usb1_pins[] = {
44 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
47 static const struct zynq_slcr_mio_get_status mio_periphs[] = {
51 ARRAY_SIZE(usb0_pins),
58 ARRAY_SIZE(usb1_pins),
64 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
66 void zynq_slcr_lock(void)
69 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
74 void zynq_slcr_unlock(void)
77 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
82 /* Reset the entire system */
83 void zynq_slcr_cpu_reset(void)
86 * Unlock the SLCR then reset the system.
87 * Note that this seems to require raw i/o
88 * functions or there's a lockup?
93 * Clear 0x0F000000 bits of reboot status register to workaround
94 * the FSBL not loading the bitstream after soft-reboot
95 * This is a temporary solution until we know more.
97 clrbits_le32(&slcr_base->reboot_status, 0xF000000);
99 writel(1, &slcr_base->pss_rst_ctrl);
102 /* Setup clk for network */
103 void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
110 printf("Non existing GEM id %d\n", gem_id);
114 ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
119 /* Configure GEM_RCLK_CTRL */
120 writel(1, &slcr_base->gem1_rclk_ctrl);
122 /* Configure GEM_RCLK_CTRL */
123 writel(1, &slcr_base->gem0_rclk_ctrl);
130 void zynq_slcr_devcfg_disable(void)
136 /* Disable AXI interface by asserting FPGA resets */
137 writel(0xF, &slcr_base->fpga_rst_ctrl);
139 /* Disable Level shifters before setting PS-PL */
140 reg_val = readl(&slcr_base->lvl_shftr_en);
142 writel(reg_val, &slcr_base->lvl_shftr_en);
144 /* Set Level Shifters DT618760 */
145 writel(0xA, &slcr_base->lvl_shftr_en);
150 void zynq_slcr_devcfg_enable(void)
154 /* Set Level Shifters DT618760 */
155 writel(0xF, &slcr_base->lvl_shftr_en);
157 /* Enable AXI interface by de-asserting FPGA resets */
158 writel(0x0, &slcr_base->fpga_rst_ctrl);
163 u32 zynq_slcr_get_boot_mode(void)
165 /* Get the bootmode register value */
166 return readl(&slcr_base->boot_mode);
169 u32 zynq_slcr_get_idcode(void)
171 return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
176 * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
178 * @periph: Name of the peripheral
180 * Returns count to indicate the number of pins configured for the
183 int zynq_slcr_get_mio_pin_status(const char *periph)
185 const struct zynq_slcr_mio_get_status *mio_ptr;
189 for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
190 if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
191 mio_ptr = &mio_periphs[i];
192 for (j = 0; j < mio_ptr->num_pins; j++) {
193 val = readl(&slcr_base->mio_pin
194 [mio_ptr->get_pins[j]]);
195 if ((val & mio_ptr->mask) == mio_ptr->check_val)