1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
10 #include <asm/arch/clk.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/ps7_init_gpl.h>
13 #include <asm/arch/sys_proto.h>
15 #define ZYNQ_SILICON_VER_MASK 0xF0000000
16 #define ZYNQ_SILICON_VER_SHIFT 28
18 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
19 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
21 .family = xilinx_zynq,
23 .operations = &zynq_op,
29 #if defined(CONFIG_FPGA)
33 } zynq_fpga_descs[] = {
47 int arch_cpu_init(void)
50 #ifndef CONFIG_SPL_BUILD
51 /* Device config APB, unlock the PCAP */
52 writel(0x757BDF0D, &devcfg_base->unlock);
53 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
55 #if (CONFIG_SYS_SDRAM_BASE == 0)
56 /* remap DDR to zero, FILTERSTART */
57 writel(0, &scu_base->filter_start);
59 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
60 writel(0x1F, &slcr_base->ocm_cfg);
61 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
62 writel(0x0, &slcr_base->fpga_rst_ctrl);
63 /* Set urgent bits with register */
64 writel(0x0, &slcr_base->ddr_urgent_sel);
65 /* Urgent write, ports S2/S3 */
66 writel(0xC, &slcr_base->ddr_urgent);
74 unsigned int zynq_get_silicon_version(void)
76 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
77 >> ZYNQ_SILICON_VER_SHIFT;
80 void reset_cpu(ulong addr)
82 zynq_slcr_cpu_reset();
87 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
88 void enable_caches(void)
90 /* Enable D-cache. I-cache is already enabled in start.S */
95 static int __maybe_unused cpu_desc_id(void)
100 idcode = zynq_slcr_get_idcode();
101 for (i = 0; zynq_fpga_descs[i].idcode; i++) {
102 if (zynq_fpga_descs[i].idcode == idcode)
109 #if defined(CONFIG_ARCH_EARLY_INIT_R)
110 int arch_early_init_r(void)
112 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
113 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
114 int cpu_id = cpu_desc_id();
119 fpga.size = zynq_fpga_descs[cpu_id].fpga_size;
120 fpga.name = zynq_fpga_descs[cpu_id].devicename;
122 fpga_add(fpga_xilinx, &fpga);
128 #ifdef CONFIG_DISPLAY_CPUINFO
129 int print_cpuinfo(void)
132 int cpu_id = cpu_desc_id();
137 version = zynq_get_silicon_version() << 1;
138 if (version > (PCW_SILICON_VERSION_3 << 1))
141 printf("CPU: Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
142 printf("Silicon: v%d.%d\n", version >> 1, version & 1);