3 * Texas Instruments <www.ti.com>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Alex Zuepke <azu@sysgo.de>
13 * (C) Copyright 2002-2004
14 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
17 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
19 * SPDX-License-Identifier: GPL-2.0+
24 #define TIMER_ENABLE (1 << 7)
25 #define TIMER_MODE_MSK (1 << 6)
26 #define TIMER_MODE_FR (0 << 6)
27 #define TIMER_MODE_PD (1 << 6)
29 #define TIMER_INT_EN (1 << 5)
30 #define TIMER_PRS_MSK (3 << 2)
31 #define TIMER_PRS_8S (1 << 3)
32 #define TIMER_SIZE_MSK (1 << 2)
33 #define TIMER_ONE_SHT (1 << 0)
39 /* 1st disable the Timer */
40 tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
41 tmr_ctrl_val &= ~TIMER_ENABLE;
42 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
45 * The Timer Control Register has one Undefined/Shouldn't Use Bit
46 * So we should do read/modify/write Operation
50 * Timer Mode : Free Running
51 * Interrupt : Disabled
52 * Prescale : 8 Stage, Clk/256
53 * Tmr Siz : 16 Bit Counter
54 * Tmr in Wrapping Mode
56 tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
57 tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
58 tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
60 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;