1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2019 Xilinx, Inc.
4 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
9 #include <asm/arch/hardware.h>
10 #include <asm/arch/sys_proto.h>
12 DECLARE_GLOBAL_DATA_PTR;
17 #define VERSAL_RPU_CFG_CPU_HALT_MASK 0x01
18 #define VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08
19 #define VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40
20 #define VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10
22 #define VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04
23 #define VERSAL_CRLAPB_RST_LPD_R50_RST_MASK 0x01
24 #define VERSAL_CRLAPB_RST_LPD_R51_RST_MASK 0x02
25 #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
26 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
28 void set_r5_halt_mode(u8 halt, u8 mode)
32 tmp = readl(&rpu_base->rpu0_cfg);
34 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
36 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
37 writel(tmp, &rpu_base->rpu0_cfg);
39 if (mode == TCM_LOCK) {
40 tmp = readl(&rpu_base->rpu1_cfg);
42 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
44 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
45 writel(tmp, &rpu_base->rpu1_cfg);
49 void set_r5_tcm_mode(u8 mode)
53 tmp = readl(&rpu_base->rpu_glbl_ctrl);
54 if (mode == TCM_LOCK) {
55 tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
56 tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
57 VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK;
59 tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
60 tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
61 VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK);
64 writel(tmp, &rpu_base->rpu_glbl_ctrl);
67 void release_r5_reset(u8 mode)
71 tmp = readl(&crlapb_base->rst_cpu_r5);
72 tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK |
73 VERSAL_CRLAPB_RST_LPD_R50_RST_MASK |
74 VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK);
77 tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK;
79 writel(tmp, &crlapb_base->rst_cpu_r5);
82 void enable_clock_r5(void)
86 tmp = readl(&crlapb_base->cpu_r5_ctrl);
87 tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
88 writel(tmp, &crlapb_base->cpu_r5_ctrl);
91 void initialize_tcm(bool mode)
94 set_r5_tcm_mode(TCM_LOCK);
95 set_r5_halt_mode(HALT, TCM_LOCK);
97 release_r5_reset(TCM_LOCK);
99 set_r5_tcm_mode(TCM_SPLIT);
100 set_r5_halt_mode(HALT, TCM_SPLIT);
102 release_r5_reset(TCM_SPLIT);
106 void tcm_init(u8 mode)
108 puts("WARNING: Initializing TCM overwrites TCM content\n");
109 initialize_tcm(mode);
110 memset((void *)VERSAL_TCM_BASE_ADDR, 0, VERSAL_TCM_SIZE);