arch/arm/mach-versal/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 - 2018 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/armv8/mmu.h>
   9 #include <asm/cache.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/hardware.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/cache.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #define VERSAL_MEM_MAP_USED     5
  18
  19 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  20
  21 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  22 #define TCM_MAP 1
  23 #else
  24 #define TCM_MAP 0
  25 #endif
  26
  27 /* +1 is end of list which needs to be empty */
  28 #define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  29
  30 static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
  31         {
  32                 .virt = 0x80000000UL,
  33                 .phys = 0x80000000UL,
  34                 .size = 0x70000000UL,
  35                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  36                          PTE_BLOCK_NON_SHARE |
  37                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  38         }, {
  39                 .virt = 0xf0000000UL,
  40                 .phys = 0xf0000000UL,
  41                 .size = 0x0fe00000UL,
  42                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  43                          PTE_BLOCK_NON_SHARE |
  44                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  45         }, {
  46                 .virt = 0x400000000UL,
  47                 .phys = 0x400000000UL,
  48                 .size = 0x200000000UL,
  49                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  50                          PTE_BLOCK_NON_SHARE |
  51                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  52         }, {
  53                 .virt = 0x600000000UL,
  54                 .phys = 0x600000000UL,
  55                 .size = 0x800000000UL,
  56                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  57                          PTE_BLOCK_INNER_SHARE
  58         }, {
  59                 .virt = 0xe00000000UL,
  60                 .phys = 0xe00000000UL,
  61                 .size = 0xf200000000UL,
  62                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  63                          PTE_BLOCK_NON_SHARE |
  64                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  65         }
  66 };
  67
  68 void mem_map_fill(void)
  69 {
  70         int banks = VERSAL_MEM_MAP_USED;
  71
  72 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  73         versal_mem_map[banks].virt = 0xffe00000UL;
  74         versal_mem_map[banks].phys = 0xffe00000UL;
  75         versal_mem_map[banks].size = 0x00200000UL;
  76         versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  77                                       PTE_BLOCK_INNER_SHARE;
  78         banks = banks + 1;
  79 #endif
  80
  81         for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  82                 /* Zero size means no more DDR that's this is end */
  83                 if (!gd->bd->bi_dram[i].size)
  84                         break;
  85
  86 #if defined(CONFIG_VERSAL_NO_DDR)
  87                 if (gd->bd->bi_dram[i].start < 0x80000000UL ||
  88                     gd->bd->bi_dram[i].start > 0x100000000UL) {
  89                         printf("Ignore caches over %llx/%llx\n",
  90                                gd->bd->bi_dram[i].start,
  91                                gd->bd->bi_dram[i].size);
  92                         continue;
  93                 }
  94 #endif
  95                 versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  96                 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  97                 versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
  98                 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  99                                               PTE_BLOCK_INNER_SHARE;
 100                 banks = banks + 1;
 101         }
 102 }
 103
 104 struct mm_region *mem_map = versal_mem_map;
 105
 106 u64 get_page_table_size(void)
 107 {
 108         return 0x14000;
 109 }
 110
 111 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
 112 int arm_reserve_mmu(void)
 113 {
 114         tcm_init(TCM_LOCK);
 115         gd->arch.tlb_size = PGTABLE_SIZE;
 116         gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
 117
 118         return 0;
 119 }
 120 #endif