2 * Copyright (C) 2013 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/linkage.h>
10 #include <asm/system.h>
12 #include <mach/sbc-regs.h>
14 /* Entry point of U-Boot main program for the secondary CPU */
15 LENTRY(secondary_entry)
16 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
17 bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable
18 mcr p15, 0, r0, c1, c0, 0
19 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
20 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
23 ldr r1, =ROM_BOOT_ROMRSV2
27 ldr r4, [r1] @ r4: entry point for secondary CPUs
31 bx r4 @ secondary CPUs jump to linux
32 ENDPROC(secondary_entry)
34 ENTRY(wakeup_secondary)
35 ldr r1, =ROM_BOOT_ROMRSV2
40 /* set entry address and send event to the secondary CPU */
41 ldr r0, =secondary_entry
43 ldr r0, [r1] @ make sure store is complete
45 0: subs r0, r0, #1 @ I don't know the reason, but without this wait
46 bne 0b @ fails to wake up the secondary CPU
49 /* wait until the secondary CPU reach to secondary_entry */
54 ENDPROC(wakeup_secondary)