1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * UniPhier SG (SoC Glue) block registers
5 * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
6 * Copyright (C) 2016-2017 Socionext Inc.
7 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
10 #ifndef UNIPHIER_SG_REGS_H
11 #define UNIPHIER_SG_REGS_H
14 #include <linux/compiler.h>
15 #define sg_base ((void __iomem *)SG_BASE)
19 #define SG_BASE 0x5f800000
22 #define SG_REVISION 0x0000
24 /* Memory Configuration */
25 #define SG_MEMCONF 0x0400
27 #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
28 #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
29 #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
30 #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
31 #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
32 #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
33 #define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
34 #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
35 #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
37 #define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
38 #define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
39 #define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
40 #define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
41 #define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
42 #define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
43 #define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
44 #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
45 #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
47 #define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
48 #define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
49 #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
50 #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
51 #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
52 #define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16))
53 #define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
54 #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
55 #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
56 /* PH1-LD6b, ProXstream2, PH1-LD20 only */
57 #define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
59 #define SG_MEMCONF_SPARSEMEM (0x1 << 4)
61 #define SG_USBPHYCTRL 0x0500
62 #define SG_ETPHYPSHUT 0x0554
63 #define SG_ETPHYCNT 0x0550
66 #define SG_PINCTRL_BASE 0x1000
68 /* PH1-Pro4, PH1-Pro5 */
69 #define SG_LOADPINCTRL 0x1700
72 #define SG_IECTRL 0x1d00
75 #define SG_PINMON0 0x00100100
76 #define SG_PINMON2 0x00100108
78 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
79 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
80 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
81 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
83 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
84 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
85 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
86 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
87 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
89 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
90 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
91 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
92 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
94 #endif /* UNIPHIER_SG_REGS_H */