1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011-2015 Panasonic Corporation
4 * Copyright (C) 2015-2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
10 #include <asm/global_data.h>
15 #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
16 #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
17 #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
19 #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
20 #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
21 #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
23 /* slower but LED works */
24 #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
25 #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
26 #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
27 #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
29 /* faster but LED does not work */
30 #define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
31 #define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
32 /* NOR flash needs more wait counts than SRAM */
33 #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
34 #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
36 int uniphier_sbc_is_enabled(void)
38 DECLARE_GLOBAL_DATA_PTR;
39 const void *fdt = gd->fdt_blob;
42 offset = fdt_node_offset_by_compatible(fdt, 0,
43 "socionext,uniphier-system-bus");
47 return fdtdec_get_is_enabled(fdt, offset);
50 static void __uniphier_sbc_init(int savepin)
53 * Only CS1 is connected to support card.
54 * BKSZ[1:0] should be set to "01".
57 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
58 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
59 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
60 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
62 writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
63 writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
64 writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
67 if (uniphier_sbc_boot_is_swapped()) {
69 * Boot Swap On: boot from external NOR/SRAM
70 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
72 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
73 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
75 writel(0x0000bc01, SBBASE0);
78 * Boot Swap Off: boot from mask ROM
79 * 0x40000000-0x41ffffff: mask ROM
80 * 0x42000000-0x43efffff: memory bank (31MB)
81 * 0x43f00000-0x43ffffff: peripherals (1MB)
83 writel(0x0000be01, SBBASE0); /* dummy */
84 writel(0x0200be01, SBBASE1);
88 void uniphier_sbc_init_admulti(void)
90 __uniphier_sbc_init(0);
93 void uniphier_sbc_init_savepin(void)
95 __uniphier_sbc_init(1);