2 * Copyright (C) 2011-2016 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 /* slower but LED works */
13 #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
14 #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
15 #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
16 #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
18 /* faster but LED does not work */
19 #define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
20 #define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
21 /* NOR flash needs more wait counts than SRAM */
22 #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
23 #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
25 int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd)
28 * Only CS1 is connected to support card.
29 * BKSZ[1:0] should be set to "01".
31 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
32 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
33 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
34 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
36 if (boot_is_swapped()) {
38 * Boot Swap On: boot from external NOR/SRAM
39 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
41 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
42 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
44 writel(0x0000bc01, SBBASE0);
47 * Boot Swap Off: boot from mask ROM
48 * 0x40000000-0x41ffffff: mask ROM
49 * 0x42000000-0x43efffff: memory bank (31MB)
50 * 0x43f00000-0x43ffffff: peripherals (1MB)
52 writel(0x0000be01, SBBASE0); /* dummy */
53 writel(0x0200be01, SBBASE1);