2 * Copyright (C) 2011-2014 Panasonic Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <mach/sc-regs.h>
10 #include <mach/sg-regs.h>
12 #undef DPLL_SSC_RATE_1PER
14 static void dpll_init(void)
20 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
21 * to FOUT ( DPLLCTRL.bit[29:20] )
23 tmp = readl(SC_DPLLCTRL);
25 #if CONFIG_DDR_FREQ == 1600
27 #elif CONFIG_DDR_FREQ == 1333
30 # error "Unsupported frequency"
35 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
37 #if defined(DPLL_SSC_RATE_1PER)
42 writel(tmp, SC_DPLLCTRL);
44 tmp = readl(SC_DPLLCTRL2);
45 tmp |= SC_DPLLCTRL2_NRSTDS;
46 writel(tmp, SC_DPLLCTRL2);
49 static void vpll_init(void)
51 u32 tmp, clk_mode_axosel;
53 /* Set VPLL27A & VPLL27B */
54 tmp = readl(SG_PINMON0);
55 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
57 #if defined(CONFIG_MACH_PH1_PRO4)
58 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
59 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
60 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
64 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
65 tmp = readl(SC_VPLL27ACTRL);
67 writel(tmp, SC_VPLL27ACTRL);
68 tmp = readl(SC_VPLL27BCTRL);
70 writel(tmp, SC_VPLL27BCTRL);
72 /* Unset VPLA_K_LD and VPLB_K_LD bit */
73 tmp = readl(SC_VPLL27ACTRL3);
75 writel(tmp, SC_VPLL27ACTRL3);
76 tmp = readl(SC_VPLL27BCTRL3);
78 writel(tmp, SC_VPLL27BCTRL3);
80 /* Set VPLA_M and VPLB_M to 0x20 */
81 tmp = readl(SC_VPLL27ACTRL2);
84 writel(tmp, SC_VPLL27ACTRL2);
85 tmp = readl(SC_VPLL27BCTRL2);
88 writel(tmp, SC_VPLL27BCTRL2);
90 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
91 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
92 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
93 tmp = readl(SC_VPLL27ACTRL3);
96 writel(tmp, SC_VPLL27ACTRL3);
97 tmp = readl(SC_VPLL27BCTRL3);
100 writel(tmp, SC_VPLL27BCTRL3);
102 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
103 tmp = readl(SC_VPLL27ACTRL3);
106 writel(tmp, SC_VPLL27ACTRL3);
107 tmp = readl(SC_VPLL27BCTRL3);
110 writel(tmp, SC_VPLL27BCTRL3);
116 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
117 tmp = readl(SC_VPLL27ACTRL3);
119 writel(tmp, SC_VPLL27ACTRL3);
120 tmp = readl(SC_VPLL27BCTRL3);
122 writel(tmp, SC_VPLL27BCTRL3);
124 /* Unset VPLA_SNRST and VPLB_SNRST bit */
125 tmp = readl(SC_VPLL27ACTRL2);
127 writel(tmp, SC_VPLL27ACTRL2);
128 tmp = readl(SC_VPLL27BCTRL2);
130 writel(tmp, SC_VPLL27BCTRL2);
132 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
133 tmp = readl(SC_VPLL27ACTRL);
135 writel(tmp, SC_VPLL27ACTRL);
136 tmp = readl(SC_VPLL27BCTRL);
138 writel(tmp, SC_VPLL27BCTRL);
147 * Wait 500 usec until dpll get stable
148 * We wait 1 usec in vpll_init() so 1 usec can be saved here.