2 * Copyright (C) 2012-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/linkage.h>
10 #include <asm/system.h>
12 #include <mach/arm-mpcore.h>
13 #include <mach/sbc-regs.h>
16 mov r8, lr @ persevere link reg across call
19 * The UniPhier Boot ROM loads SPL code to the L2 cache.
20 * But CPUs can only do instruction fetch now because start.S has
21 * cleared C and M bits.
22 * First we need to turn on MMU and Dcache again to get back
25 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
26 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
27 mcr p15, 0, r0, c1, c0, 0
29 #ifdef CONFIG_DEBUG_LL
30 bl setup_lowlevel_debug
34 * Now we are using the page table embedded in the Boot ROM.
35 * It is not handy since it is not a straight mapped table for sLD3.
36 * What we need to do next is to switch over to the page table in SPL.
38 ldr r3, =init_page_table @ page table must be 16KB aligned
40 /* Disable MMU and Dcache before switching Page Table */
41 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
42 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
43 mcr p15, 0, r0, c1, c0, 0
47 #ifdef CONFIG_UNIPHIER_SMP
49 * ACTLR (Auxiliary Control Register) for Cortex-A9
51 * bit[8] Alloc in one way
52 * bit[7] EXCL (Exclusive cache bit)
54 * bit[3] Write full line of zeros mode
55 * bit[2] L1 Prefetch enable
56 * bit[1] L2 prefetch enable
57 * bit[0] FW (Cache and TLB maintenance broadcast)
59 mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
60 orr r0, r0, #0x41 @ enable SMP, FW bit
61 mcr p15, 0, r0, c1, c0, 1
63 /* branch by CPU ID */
64 mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
68 ldr r1, =ROM_BOOT_ROMRSV2
75 bx r0 @ r0: entry point of U-Boot main for the secondary CPU
77 ldr r1, =ROM_BOOT_ROMRSV2
78 ldr r0, =_start @ entry for the secondary CPU
80 ldr r0, [r1] @ make sure str is complete before sev
81 sev @ kick the sedoncary CPU
82 mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
83 bfc r1, #0, #13 @ clear bit 12-0
85 str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
86 mov r0, #1 @ SCU enable
87 str r0, [r1, #SCU_CTRL] @ SCU Control Register
90 bl setup_init_ram @ RAM area for temporary stack pointer
92 mov lr, r8 @ restore link
93 mov pc, lr @ back to my caller
94 ENDPROC(lowlevel_init)
97 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
99 orr r0, r0, #0x20 @ disable TTBR1
100 mcr p15, 0, r0, c2, c0, 2
102 orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
103 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
106 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
108 mov r0, #-1 @ manager for all domains (No permission check)
109 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
115 * TLBs was already invalidated in "../start.S"
116 * So, we don't need to invalidate it here.
118 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
119 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
120 mcr p15, 0, r0, c1, c0, 0
125 #include <mach/ssc-regs.h>
127 #define BOOT_RAM_SIZE (SSC_WAY_SIZE)
128 #define BOOT_WAY_BITS (0x00000100) /* way 8 */
130 ENTRY(setup_init_ram)
132 * Touch to zero for the boot way
136 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
138 ldr r0, = 0x00408006 @ touch to zero with address range
141 ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address
144 ldr r0, = BOOT_RAM_SIZE
147 ldr r0, = BOOT_WAY_BITS
152 cmp r0, #0 @ check if the command is successfully set
153 bne 0b @ try again if an error occurres
159 bne 1b @ wait until the operation is completed
160 str r0, [r1] @ clear the complete notification flag
163 ENDPROC(setup_init_ram)