arch/arm/mach-uniphier/dram/umc-ph1-ld4.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/sizes.h>
  11
  12 #include "../init.h"
  13 #include "ddrphy-regs.h"
  14 #include "umc-regs.h"
  15
  16 enum dram_freq {
  17         DRAM_FREQ_1333M,
  18         DRAM_FREQ_1600M,
  19         DRAM_FREQ_NR,
  20 };
  21
  22 enum dram_size {
  23         DRAM_SZ_128M,
  24         DRAM_SZ_256M,
  25         DRAM_SZ_NR,
  26 };
  27
  28 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
  29 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
  30 static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
  31         {0x00240512, 0x00350512},
  32         {0x002b0617, 0x003f0617},
  33 };
  34 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
  35 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
  36
  37 static void umc_start_ssif(void __iomem *ssif_base)
  38 {
  39         writel(0x00000000, ssif_base + 0x0000b004);
  40         writel(0xffffffff, ssif_base + 0x0000c004);
  41         writel(0x000fffcf, ssif_base + 0x0000c008);
  42         writel(0x00000001, ssif_base + 0x0000b000);
  43         writel(0x00000001, ssif_base + 0x0000c000);
  44         writel(0x03010101, ssif_base + UMC_MDMCHSEL);
  45         writel(0x03010100, ssif_base + UMC_DMDCHSEL);
  46
  47         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
  48         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
  49         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
  50         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
  51         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
  52         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
  53         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
  54         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
  55         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
  56         writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
  57
  58         writel(0x00000001, ssif_base + UMC_CPURST);
  59         writel(0x00000001, ssif_base + UMC_IDSRST);
  60         writel(0x00000001, ssif_base + UMC_IXMRST);
  61         writel(0x00000001, ssif_base + UMC_MDMRST);
  62         writel(0x00000001, ssif_base + UMC_MDDRST);
  63         writel(0x00000001, ssif_base + UMC_SIORST);
  64         writel(0x00000001, ssif_base + UMC_VIORST);
  65         writel(0x00000001, ssif_base + UMC_FRCRST);
  66         writel(0x00000001, ssif_base + UMC_RGLRST);
  67         writel(0x00000001, ssif_base + UMC_AIORST);
  68         writel(0x00000001, ssif_base + UMC_DMDRST);
  69 }
  70
  71 static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
  72                              int size, int freq)
  73 {
  74         enum dram_freq freq_e;
  75         enum dram_size size_e;
  76
  77         switch (freq) {
  78         case 1333:
  79                 freq_e = DRAM_FREQ_1333M;
  80                 break;
  81         case 1600:
  82                 freq_e = DRAM_FREQ_1600M;
  83                 break;
  84         default:
  85                 pr_err("unsupported DRAM frequency %d MHz\n", freq);
  86                 return -EINVAL;
  87         }
  88
  89         switch (size) {
  90         case 0:
  91                 return 0;
  92         case 1:
  93                 size_e = DRAM_SZ_128M;
  94                 break;
  95         case 2:
  96                 size_e = DRAM_SZ_256M;
  97                 break;
  98         default:
  99                 pr_err("unsupported DRAM size\n");
 100                 return -EINVAL;
 101         }
 102
 103         writel(umc_cmdctla_plus[freq_e], dramcont + UMC_CMDCTLA);
 104         writel(umc_cmdctlb_plus[freq_e], dramcont + UMC_CMDCTLB);
 105         writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA);
 106         writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB);
 107         writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0);
 108         writel(0x04060806, dramcont + UMC_WDATACTL_D0);
 109         writel(0x04a02000, dramcont + UMC_DATASET);
 110         writel(0x00000000, ca_base + 0x2300);
 111         writel(0x00400020, dramcont + UMC_DCCGCTL);
 112         writel(0x00000003, dramcont + 0x7000);
 113         writel(0x0000000f, dramcont + 0x8000);
 114         writel(0x000000c3, dramcont + 0x8004);
 115         writel(0x00000071, dramcont + 0x8008);
 116         writel(0x0000003b, dramcont + UMC_DICGCTLA);
 117         writel(0x020a0808, dramcont + UMC_DICGCTLB);
 118         writel(0x00000004, dramcont + UMC_FLOWCTLG);
 119         writel(0x80000201, ca_base + 0xc20);
 120         writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
 121         writel(0x00200000, dramcont + UMC_FLOWCTLB);
 122         writel(0x00004444, dramcont + UMC_FLOWCTLC);
 123         writel(0x200a0a00, dramcont + UMC_SPCSETB);
 124         writel(0x00000000, dramcont + UMC_SPCSETD);
 125         writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
 126
 127         return 0;
 128 }
 129
 130 static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
 131 {
 132         void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
 133         void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
 134         void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
 135         void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
 136         void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
 137         void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
 138         void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
 139
 140         umc_dram_init_start(dramcont0);
 141         umc_dram_init_start(dramcont1);
 142         umc_dram_init_poll(dramcont0);
 143         umc_dram_init_poll(dramcont1);
 144
 145         writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 146
 147         ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
 148
 149         ddrphy_prepare_training(phy0_0, 0);
 150         ddrphy_training(phy0_0);
 151
 152         writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 153
 154         ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
 155
 156         ddrphy_prepare_training(phy1_0, 1);
 157         ddrphy_training(phy1_0);
 158
 159         umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
 160         umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
 161
 162         umc_start_ssif(ssif_base);
 163
 164         return 0;
 165 }
 166
 167 int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
 168 {
 169         if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) &&
 170             (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) &&
 171             (bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
 172             bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
 173                 return umc_init_sub(bd->dram_freq,
 174                                     bd->dram_ch[0].size / SZ_128M,
 175                                     bd->dram_ch[1].size / SZ_128M,
 176                                     bd->dram_ddr3plus);
 177         } else {
 178                 pr_err("Unsupported DDR configuration\n");
 179                 return -EINVAL;
 180         }
 181 }