arch/arm/mach-uniphier/dram/ddrphy-ld4.c

   1 /*
   2  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/types.h>
  10 #include <linux/io.h>
  11
  12 #include "ddrphy-regs.h"
  13
  14 enum dram_freq {
  15         DRAM_FREQ_1333M,
  16         DRAM_FREQ_1600M,
  17         DRAM_FREQ_NR,
  18 };
  19
  20 static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
  21 static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
  22 static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
  23 static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
  24 static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
  25 static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
  26 static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
  27 static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
  28 static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
  29
  30 int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
  31                              bool ddr3plus)
  32 {
  33         enum dram_freq freq_e;
  34         u32 tmp;
  35
  36         switch (freq) {
  37         case 1333:
  38                 freq_e = DRAM_FREQ_1333M;
  39                 break;
  40         case 1600:
  41                 freq_e = DRAM_FREQ_1600M;
  42                 break;
  43         default:
  44                 printf("unsupported DRAM frequency %d MHz\n", freq);
  45                 return -EINVAL;
  46         }
  47
  48         writel(0x0300c473, &phy->pgcr[1]);
  49         writel(ddrphy_ptr0[freq_e], &phy->ptr[0]);
  50         writel(ddrphy_ptr1[freq_e], &phy->ptr[1]);
  51         writel(0x00083DEF, &phy->ptr[2]);
  52         writel(ddrphy_ptr3[freq_e], &phy->ptr[3]);
  53         writel(ddrphy_ptr4[freq_e], &phy->ptr[4]);
  54         writel(0xF004001A, &phy->dsgcr);
  55
  56         /* change the value of the on-die pull-up/pull-down registors */
  57         tmp = readl(&phy->dxccr);
  58         tmp &= ~0x0ee0;
  59         tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
  60         writel(tmp, &phy->dxccr);
  61
  62         writel(0x0000040B, &phy->dcr);
  63         writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]);
  64         writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]);
  65         writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]);
  66         writel(ddrphy_mr0[freq_e], &phy->mr0);
  67         writel(0x00000006, &phy->mr1);
  68         writel(ddrphy_mr2[freq_e], &phy->mr2);
  69         writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
  70
  71         while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
  72                 ;
  73
  74         writel(0x0300C473, &phy->pgcr[1]);
  75         writel(0x0000005D, &phy->zq[0].cr[1]);
  76
  77         return 0;
  78 }