arch/arm/mach-uniphier/dram/cmd_ddrphy.c

   1 /*
   2  * Copyright (C) 2014      Panasonic Corporation
   3  * Copyright (C) 2015-2017 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <linux/io.h>
  11 #include <linux/sizes.h>
  12
  13 #include "../soc-info.h"
  14 #include "ddrphy-regs.h"
  15
  16 /* Select either decimal or hexadecimal */
  17 #if 1
  18 #define PRINTF_FORMAT "%2d"
  19 #else
  20 #define PRINTF_FORMAT "%02x"
  21 #endif
  22 /* field separator */
  23 #define FS "   "
  24
  25 #define ptr_to_uint(p)  ((unsigned int)(unsigned long)(p))
  26
  27 #define UNIPHIER_MAX_NR_DDRPHY          4
  28
  29 struct uniphier_ddrphy_param {
  30         unsigned int soc_id;
  31         unsigned int nr_phy;
  32         struct {
  33                 resource_size_t base;
  34                 unsigned int nr_dx;
  35         } phy[UNIPHIER_MAX_NR_DDRPHY];
  36 };
  37
  38 static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
  39         {
  40                 .soc_id = UNIPHIER_LD4_ID,
  41                 .nr_phy = 2,
  42                 .phy = {
  43                         { .base = 0x5bc01000, .nr_dx = 2, },
  44                         { .base = 0x5be01000, .nr_dx = 2, },
  45                 },
  46         },
  47         {
  48                 .soc_id = UNIPHIER_PRO4_ID,
  49                 .nr_phy = 4,
  50                 .phy = {
  51                         { .base = 0x5bc01000, .nr_dx = 2, },
  52                         { .base = 0x5bc02000, .nr_dx = 2, },
  53                         { .base = 0x5be01000, .nr_dx = 2, },
  54                         { .base = 0x5be02000, .nr_dx = 2, },
  55                 },
  56         },
  57         {
  58                 .soc_id = UNIPHIER_SLD8_ID,
  59                 .nr_phy = 2,
  60                 .phy = {
  61                         { .base = 0x5bc01000, .nr_dx = 2, },
  62                         { .base = 0x5be01000, .nr_dx = 2, },
  63                 },
  64         },
  65         {
  66                 .soc_id = UNIPHIER_LD11_ID,
  67                 .nr_phy = 1,
  68                 .phy = {
  69                         { .base = 0x5bc01000, .nr_dx = 4, },
  70                 },
  71         },
  72 };
  73 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
  74
  75 static void print_bdl(void __iomem *reg, int n)
  76 {
  77         u32 val = readl(reg);
  78         int i;
  79
  80         for (i = 0; i < n; i++)
  81                 printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
  82 }
  83
  84 static void dump_loop(const struct uniphier_ddrphy_param *param,
  85                       void (*callback)(void __iomem *))
  86 {
  87         void __iomem *phy_base, *dx_base;
  88         int phy, dx;
  89
  90         for (phy = 0; phy < param->nr_phy; phy++) {
  91                 phy_base = ioremap(param->phy[phy].base, SZ_4K);
  92                 dx_base = phy_base + PHY_DX_BASE;
  93
  94                 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
  95                         printf("PHY%dDX%d:", phy, dx);
  96                         (*callback)(dx_base);
  97                         dx_base += PHY_DX_STRIDE;
  98                         printf("\n");
  99                 }
 100
 101                 iounmap(phy_base);
 102         }
 103 }
 104
 105 static void __wbdl_dump(void __iomem *dx_base)
 106 {
 107         print_bdl(dx_base + PHY_DX_BDLR0, 5);
 108         print_bdl(dx_base + PHY_DX_BDLR1, 5);
 109
 110         printf(FS "(+" PRINTF_FORMAT ")",
 111                readl(dx_base + PHY_DX_LCDLR1) & 0xff);
 112 }
 113
 114 static void wbdl_dump(const struct uniphier_ddrphy_param *param)
 115 {
 116         printf("\n--- Write Bit Delay Line ---\n");
 117         printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  DQS  (WDQD)\n");
 118
 119         dump_loop(param, &__wbdl_dump);
 120 }
 121
 122 static void __rbdl_dump(void __iomem *dx_base)
 123 {
 124         print_bdl(dx_base + PHY_DX_BDLR3, 5);
 125         print_bdl(dx_base + PHY_DX_BDLR4, 4);
 126
 127         printf(FS "(+" PRINTF_FORMAT ")",
 128                (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
 129 }
 130
 131 static void rbdl_dump(const struct uniphier_ddrphy_param *param)
 132 {
 133         printf("\n--- Read Bit Delay Line ---\n");
 134         printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  (RDQSD)\n");
 135
 136         dump_loop(param, &__rbdl_dump);
 137 }
 138
 139 static void __wld_dump(void __iomem *dx_base)
 140 {
 141         int rank;
 142         u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
 143         u32 gtr = readl(dx_base + PHY_DX_GTR);
 144
 145         for (rank = 0; rank < 4; rank++) {
 146                 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
 147                 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
 148
 149                 printf(FS PRINTF_FORMAT "%sT", wld,
 150                        wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
 151         }
 152 }
 153
 154 static void wld_dump(const struct uniphier_ddrphy_param *param)
 155 {
 156         printf("\n--- Write Leveling Delay ---\n");
 157         printf("           Rank0   Rank1   Rank2   Rank3\n");
 158
 159         dump_loop(param, &__wld_dump);
 160 }
 161
 162 static void __dqsgd_dump(void __iomem *dx_base)
 163 {
 164         int rank;
 165         u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
 166         u32 gtr = readl(dx_base + PHY_DX_GTR);
 167
 168         for (rank = 0; rank < 4; rank++) {
 169                 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
 170                 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
 171
 172                 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
 173         }
 174 }
 175
 176 static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
 177 {
 178         printf("\n--- DQS Gating Delay ---\n");
 179         printf("           Rank0   Rank1   Rank2   Rank3\n");
 180
 181         dump_loop(param, &__dqsgd_dump);
 182 }
 183
 184 static void __mdl_dump(void __iomem *dx_base)
 185 {
 186         int i;
 187         u32 mdl = readl(dx_base + PHY_DX_MDLR);
 188
 189         for (i = 0; i < 3; i++)
 190                 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
 191 }
 192
 193 static void mdl_dump(const struct uniphier_ddrphy_param *param)
 194 {
 195         printf("\n--- Master Delay Line ---\n");
 196         printf("          IPRD TPRD MDLD\n");
 197
 198         dump_loop(param, &__mdl_dump);
 199 }
 200
 201 #define REG_DUMP(x)                                                     \
 202         { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst;    \
 203                 printf("%3d: %-10s: %08x : %08x\n",                     \
 204                        ofst >> PHY_REG_SHIFT, #x,                       \
 205                        ptr_to_uint(reg), readl(reg)); }
 206
 207 #define DX_REG_DUMP(dx, x)                                              \
 208         { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) +               \
 209                         PHY_DX_## x;                                    \
 210                 void __iomem *reg = phy_base + ofst;                    \
 211                 printf("%3d: DX%d%-7s: %08x : %08x\n",                  \
 212                        ofst >> PHY_REG_SHIFT, (dx), #x,                 \
 213                        ptr_to_uint(reg), readl(reg)); }
 214
 215 static void reg_dump(const struct uniphier_ddrphy_param *param)
 216 {
 217         void __iomem *phy_base;
 218         int phy, dx;
 219
 220         printf("\n--- DDR PHY registers ---\n");
 221
 222         for (phy = 0; phy < param->nr_phy; phy++) {
 223                 phy_base = ioremap(param->phy[phy].base, SZ_4K);
 224
 225                 printf("== PHY%d (base: %08x) ==\n",
 226                        phy, ptr_to_uint(phy_base));
 227                 printf(" No: Name      : Address  : Data\n");
 228
 229                 REG_DUMP(RIDR);
 230                 REG_DUMP(PIR);
 231                 REG_DUMP(PGCR0);
 232                 REG_DUMP(PGCR1);
 233                 REG_DUMP(PGSR0);
 234                 REG_DUMP(PGSR1);
 235                 REG_DUMP(PLLCR);
 236                 REG_DUMP(PTR0);
 237                 REG_DUMP(PTR1);
 238                 REG_DUMP(PTR2);
 239                 REG_DUMP(PTR3);
 240                 REG_DUMP(PTR4);
 241                 REG_DUMP(ACMDLR);
 242                 REG_DUMP(ACBDLR);
 243                 REG_DUMP(DXCCR);
 244                 REG_DUMP(DSGCR);
 245                 REG_DUMP(DCR);
 246                 REG_DUMP(DTPR0);
 247                 REG_DUMP(DTPR1);
 248                 REG_DUMP(DTPR2);
 249                 REG_DUMP(MR0);
 250                 REG_DUMP(MR1);
 251                 REG_DUMP(MR2);
 252                 REG_DUMP(MR3);
 253
 254                 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
 255                         DX_REG_DUMP(dx, GCR);
 256                         DX_REG_DUMP(dx, GTR);
 257                 }
 258
 259                 iounmap(phy_base);
 260         }
 261 }
 262
 263 static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 264 {
 265         const struct uniphier_ddrphy_param *param;
 266         char *cmd;
 267
 268         param = uniphier_get_ddrphy_param();
 269         if (!param) {
 270                 printf("unsupported SoC\n");
 271                 return CMD_RET_FAILURE;
 272         }
 273
 274         if (argc == 1)
 275                 cmd = "all";
 276         else
 277                 cmd = argv[1];
 278
 279         if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
 280                 wbdl_dump(param);
 281
 282         if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
 283                 rbdl_dump(param);
 284
 285         if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
 286                 wld_dump(param);
 287
 288         if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
 289                 dqsgd_dump(param);
 290
 291         if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
 292                 mdl_dump(param);
 293
 294         if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
 295                 reg_dump(param);
 296
 297         return CMD_RET_SUCCESS;
 298 }
 299
 300 U_BOOT_CMD(
 301         ddr,    2,      1,      do_ddr,
 302         "UniPhier DDR PHY parameters dumper",
 303         "- dump all of the following\n"
 304         "ddr wbdl - dump Write Bit Delay\n"
 305         "ddr rbdl - dump Read Bit Delay\n"
 306         "ddr wld - dump Write Leveling\n"
 307         "ddr dqsgd - dump DQS Gating Delay\n"
 308         "ddr mdl - dump Master Delay Line\n"
 309         "ddr reg - dump registers\n"
 310 );