2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/printk.h>
13 #include <linux/sizes.h>
15 #include "../soc-info.h"
16 #include "ddrphy-regs.h"
18 /* Select either decimal or hexadecimal */
20 #define PRINTF_FORMAT "%2d"
22 #define PRINTF_FORMAT "%02x"
27 #define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
29 #define UNIPHIER_MAX_NR_DDRPHY 4
31 struct uniphier_ddrphy_param {
37 } phy[UNIPHIER_MAX_NR_DDRPHY];
40 static const struct uniphier_ddrphy_param uniphier_ddrphy_param[] = {
42 .soc_id = UNIPHIER_LD4_ID,
45 { .base = 0x5bc01000, .nr_dx = 2, },
46 { .base = 0x5be01000, .nr_dx = 2, },
50 .soc_id = UNIPHIER_PRO4_ID,
53 { .base = 0x5bc01000, .nr_dx = 2, },
54 { .base = 0x5bc02000, .nr_dx = 2, },
55 { .base = 0x5be01000, .nr_dx = 2, },
56 { .base = 0x5be02000, .nr_dx = 2, },
60 .soc_id = UNIPHIER_SLD8_ID,
63 { .base = 0x5bc01000, .nr_dx = 2, },
64 { .base = 0x5be01000, .nr_dx = 2, },
68 .soc_id = UNIPHIER_LD11_ID,
71 { .base = 0x5bc01000, .nr_dx = 4, },
75 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrphy_param, uniphier_ddrphy_param)
77 static void print_bdl(void __iomem *reg, int n)
82 for (i = 0; i < n; i++)
83 printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
86 static void dump_loop(const struct uniphier_ddrphy_param *param,
87 void (*callback)(void __iomem *))
89 void __iomem *phy_base, *dx_base;
92 for (phy = 0; phy < param->nr_phy; phy++) {
93 phy_base = ioremap(param->phy[phy].base, SZ_4K);
94 dx_base = phy_base + PHY_DX_BASE;
96 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
97 printf("PHY%dDX%d:", phy, dx);
99 dx_base += PHY_DX_STRIDE;
107 static void __wbdl_dump(void __iomem *dx_base)
109 print_bdl(dx_base + PHY_DX_BDLR0, 5);
110 print_bdl(dx_base + PHY_DX_BDLR1, 5);
112 printf(FS "(+" PRINTF_FORMAT ")",
113 readl(dx_base + PHY_DX_LCDLR1) & 0xff);
116 static void wbdl_dump(const struct uniphier_ddrphy_param *param)
118 printf("\n--- Write Bit Delay Line ---\n");
119 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
121 dump_loop(param, &__wbdl_dump);
124 static void __rbdl_dump(void __iomem *dx_base)
126 print_bdl(dx_base + PHY_DX_BDLR3, 5);
127 print_bdl(dx_base + PHY_DX_BDLR4, 4);
129 printf(FS "(+" PRINTF_FORMAT ")",
130 (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
133 static void rbdl_dump(const struct uniphier_ddrphy_param *param)
135 printf("\n--- Read Bit Delay Line ---\n");
136 printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
138 dump_loop(param, &__rbdl_dump);
141 static void __wld_dump(void __iomem *dx_base)
144 u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
145 u32 gtr = readl(dx_base + PHY_DX_GTR);
147 for (rank = 0; rank < 4; rank++) {
148 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
149 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
151 printf(FS PRINTF_FORMAT "%sT", wld,
152 wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
156 static void wld_dump(const struct uniphier_ddrphy_param *param)
158 printf("\n--- Write Leveling Delay ---\n");
159 printf(" Rank0 Rank1 Rank2 Rank3\n");
161 dump_loop(param, &__wld_dump);
164 static void __dqsgd_dump(void __iomem *dx_base)
167 u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
168 u32 gtr = readl(dx_base + PHY_DX_GTR);
170 for (rank = 0; rank < 4; rank++) {
171 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
172 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
174 printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
178 static void dqsgd_dump(const struct uniphier_ddrphy_param *param)
180 printf("\n--- DQS Gating Delay ---\n");
181 printf(" Rank0 Rank1 Rank2 Rank3\n");
183 dump_loop(param, &__dqsgd_dump);
186 static void __mdl_dump(void __iomem *dx_base)
189 u32 mdl = readl(dx_base + PHY_DX_MDLR);
191 for (i = 0; i < 3; i++)
192 printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
195 static void mdl_dump(const struct uniphier_ddrphy_param *param)
197 printf("\n--- Master Delay Line ---\n");
198 printf(" IPRD TPRD MDLD\n");
200 dump_loop(param, &__mdl_dump);
203 #define REG_DUMP(x) \
204 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
205 printf("%3d: %-10s: %08x : %08x\n", \
206 ofst >> PHY_REG_SHIFT, #x, \
207 ptr_to_uint(reg), readl(reg)); }
209 #define DX_REG_DUMP(dx, x) \
210 { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
212 void __iomem *reg = phy_base + ofst; \
213 printf("%3d: DX%d%-7s: %08x : %08x\n", \
214 ofst >> PHY_REG_SHIFT, (dx), #x, \
215 ptr_to_uint(reg), readl(reg)); }
217 static void reg_dump(const struct uniphier_ddrphy_param *param)
219 void __iomem *phy_base;
222 printf("\n--- DDR PHY registers ---\n");
224 for (phy = 0; phy < param->nr_phy; phy++) {
225 phy_base = ioremap(param->phy[phy].base, SZ_4K);
227 printf("== PHY%d (base: %08x) ==\n",
228 phy, ptr_to_uint(phy_base));
229 printf(" No: Name : Address : Data\n");
256 for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
257 DX_REG_DUMP(dx, GCR);
258 DX_REG_DUMP(dx, GTR);
265 static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
267 const struct uniphier_ddrphy_param *param;
270 param = uniphier_get_ddrphy_param();
272 pr_err("unsupported SoC\n");
273 return CMD_RET_FAILURE;
281 if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
284 if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
287 if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
290 if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
293 if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
296 if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
299 return CMD_RET_SUCCESS;
304 "UniPhier DDR PHY parameters dumper",
305 "- dump all of the following\n"
306 "ddr wbdl - dump Write Bit Delay\n"
307 "ddr rbdl - dump Read Bit Delay\n"
308 "ddr wld - dump Write Leveling\n"
309 "ddr dqsgd - dump DQS Gating Delay\n"
310 "ddr mdl - dump Master Delay Line\n"
311 "ddr reg - dump registers\n"