arch/arm/mach-uniphier/debug_ll.S

   1 /*
   2  * On-chip UART initializaion for low-level debugging
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <linux/serial_reg.h>
  10 #include <linux/linkage.h>
  11 #include <mach/bcu-regs.h>
  12 #include <mach/sc-regs.h>
  13 #include <mach/sg-regs.h>
  14
  15 #if !defined(CONFIG_DEBUG_SEMIHOSTING)
  16 #include CONFIG_DEBUG_LL_INCLUDE
  17 #endif
  18
  19 #define BAUDRATE                115200
  20 #define DIV_ROUND(x, d)         (((x) + ((d) / 2)) / (d))
  21
  22 ENTRY(debug_ll_init)
  23         ldr             r0, =SG_REVISION
  24         ldr             r1, [r0]
  25         and             r1, r1, #SG_REVISION_TYPE_MASK
  26         mov             r1, r1, lsr #SG_REVISION_TYPE_SHIFT
  27
  28 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
  29 #define PH1_SLD3_UART_CLK               36864000
  30         cmp             r1, #0x25
  31         bne             ph1_sld3_end
  32
  33         sg_set_pinsel   64, 1, 4, 4, r0, r1     @ TXD0 -> TXD0
  34
  35         ldr             r0, =BCSCR5
  36         ldr             r1, =0x24440000
  37         str             r1, [r0]
  38
  39         ldr             r0, =SC_CLKCTRL
  40         ldr             r1, [r0]
  41         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
  42         str             r1, [r0]
  43
  44         ldr             r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE)
  45
  46         b               init_uart
  47 ph1_sld3_end:
  48 #endif
  49 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
  50 #define PH1_LD4_UART_CLK                36864000
  51         cmp             r1, #0x26
  52         bne             ph1_ld4_end
  53
  54         ldr             r0, =SG_IECTRL
  55         ldr             r1, [r0]
  56         orr             r1, r1, #1
  57         str             r1, [r0]
  58
  59         sg_set_pinsel   88, 1, 8, 4, r0, r1     @ HSDOUT6 -> TXD0
  60
  61         ldr             r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE)
  62
  63         b               init_uart
  64 ph1_ld4_end:
  65 #endif
  66 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
  67 #define PH1_PRO4_UART_CLK               73728000
  68         cmp             r1, #0x28
  69         bne             ph1_pro4_end
  70
  71         sg_set_pinsel   128, 0, 4, 8, r0, r1    @ TXD0 -> TXD0
  72
  73         ldr             r0, =SG_LOADPINCTRL
  74         mov             r1, #1
  75         str             r1, [r0]
  76
  77         ldr             r0, =SC_CLKCTRL
  78         ldr             r1, [r0]
  79         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
  80         str             r1, [r0]
  81
  82         ldr             r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE)
  83
  84         b               init_uart
  85 ph1_pro4_end:
  86 #endif
  87 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
  88 #define PH1_SLD8_UART_CLK               80000000
  89         cmp             r1, #0x29
  90         bne             ph1_sld8_end
  91
  92         ldr             r0, =SG_IECTRL
  93         ldr             r1, [r0]
  94         orr             r1, r1, #1
  95         str             r1, [r0]
  96
  97         sg_set_pinsel   70, 3, 8, 4, r0, r1     @ HSDOUT0 -> TXD0
  98
  99         ldr             r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE)
 100
 101         b               init_uart
 102 ph1_sld8_end:
 103 #endif
 104 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
 105 #define PH1_PRO5_UART_CLK               73728000
 106         cmp             r1, #0x2A
 107         bne             ph1_pro5_end
 108
 109         sg_set_pinsel   47, 0, 4, 8, r0, r1     @ TXD0 -> TXD0
 110         sg_set_pinsel   49, 0, 4, 8, r0, r1     @ TXD1 -> TXD1
 111         sg_set_pinsel   51, 0, 4, 8, r0, r1     @ TXD2 -> TXD2
 112         sg_set_pinsel   53, 0, 4, 8, r0, r1     @ TXD3 -> TXD3
 113
 114         ldr             r0, =SG_LOADPINCTRL
 115         mov             r1, #1
 116         str             r1, [r0]
 117
 118         ldr             r0, =SC_CLKCTRL
 119         ldr             r1, [r0]
 120         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
 121         str             r1, [r0]
 122
 123         ldr             r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
 124
 125         b               init_uart
 126 ph1_pro5_end:
 127 #endif
 128 #if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
 129 #define PROXSTREAM2_UART_CLK            88900000
 130         cmp             r1, #0x2E
 131         bne             proxstream2_end
 132
 133         ldr             r0, =SG_IECTRL
 134         ldr             r1, [r0]
 135         orr             r1, r1, #1
 136         str             r1, [r0]
 137
 138         sg_set_pinsel   217, 8, 8, 4, r0, r1    @ TXD0 -> TXD0
 139         sg_set_pinsel   115, 8, 8, 4, r0, r1    @ TXD1 -> TXD1
 140         sg_set_pinsel   113, 8, 8, 4, r0, r1    @ TXD2 -> TXD2
 141         sg_set_pinsel   219, 8, 8, 4, r0, r1    @ TXD3 -> TXD3
 142
 143         ldr             r0, =SC_CLKCTRL
 144         ldr             r1, [r0]
 145         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
 146         str             r1, [r0]
 147
 148         ldr             r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
 149
 150         b               init_uart
 151 proxstream2_end:
 152 #endif
 153 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
 154 #define PH1_LD6B_UART_CLK               88900000
 155         cmp             r1, #0x2F
 156         bne             ph1_ld6b_end
 157
 158         ldr             r0, =SG_IECTRL
 159         ldr             r1, [r0]
 160         orr             r1, r1, #1
 161         str             r1, [r0]
 162
 163         sg_set_pinsel   135, 3, 8, 4, r0, r1    @ PORT10 -> TXD0
 164         sg_set_pinsel   115, 0, 8, 4, r0, r1    @ TXD1 -> TXD1
 165         sg_set_pinsel   113, 2, 8, 4, r0, r1    @ SBO0 -> TXD2
 166
 167         ldr             r0, =SC_CLKCTRL
 168         ldr             r1, [r0]
 169         orr             r1, r1, #SC_CLKCTRL_CEN_PERI
 170         str             r1, [r0]
 171
 172         ldr             r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
 173
 174         b               init_uart
 175 ph1_ld6b_end:
 176 #endif
 177
 178 init_uart:
 179         addruart        r0, r1, r2
 180         mov             r1, #UART_LCR_WLEN8 << 8
 181         str             r1, [r0, #0x10]
 182         str             r3, [r0, #0x24]
 183
 184         mov             pc, lr
 185 ENDPROC(debug_ll_init)