1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
7 #include <linux/delay.h>
11 #include "../sc-regs.h"
12 #include "../sg-regs.h"
15 static void upll_init(void)
17 u32 tmp, clk_mode_upll, clk_mode_axosel;
19 tmp = readl(sg_base + SG_PINMON0);
20 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
21 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
23 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
24 tmp = readl(sc_base + SC_UPLLCTRL);
26 writel(tmp, sc_base + SC_UPLLCTRL);
28 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
29 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
30 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
35 /* AXO: default 24.576MHz */
41 writel(tmp, sc_base + SC_UPLLCTRL);
43 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
45 writel(tmp, sc_base + SC_UPLLCTRL);
50 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
52 writel(tmp, sc_base + SC_UPLLCTRL);
55 static void vpll_init(void)
57 u32 tmp, clk_mode_axosel;
59 tmp = readl(sg_base + SG_PINMON0);
60 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
62 /* set 1 to VPLA27WP and VPLA27WP */
63 tmp = readl(sc_base + SC_VPLL27ACTRL);
65 writel(tmp, sc_base + SC_VPLL27ACTRL);
66 tmp = readl(sc_base + SC_VPLL27BCTRL);
68 writel(tmp, sc_base + SC_VPLL27BCTRL);
70 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
71 tmp = readl(sc_base + SC_VPLL27ACTRL3);
73 writel(tmp, sc_base + SC_VPLL27ACTRL3);
74 tmp = readl(sc_base + SC_VPLL27BCTRL3);
76 writel(tmp, sc_base + SC_VPLL27BCTRL3);
78 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
79 tmp = readl(sc_base + SC_VPLL27ACTRL2);
81 writel(tmp, sc_base + SC_VPLL27ACTRL2);
82 tmp = readl(sc_base + SC_VPLL27BCTRL2);
84 writel(tmp, sc_base + SC_VPLL27BCTRL2);
86 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
87 tmp = readl(sc_base + SC_VPLL27ACTRL2);
90 writel(tmp, sc_base + SC_VPLL27ACTRL2);
91 tmp = readl(sc_base + SC_VPLL27BCTRL2);
94 writel(tmp, sc_base + SC_VPLL27BCTRL2);
96 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
97 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
99 tmp = readl(sc_base + SC_VPLL27ACTRL3);
102 writel(tmp, sc_base + SC_VPLL27ACTRL3);
103 tmp = readl(sc_base + SC_VPLL27BCTRL3);
106 writel(tmp, sc_base + SC_VPLL27BCTRL3);
108 /* AXO: default 24.576MHz */
109 tmp = readl(sc_base + SC_VPLL27ACTRL3);
112 writel(tmp, sc_base + SC_VPLL27ACTRL3);
113 tmp = readl(sc_base + SC_VPLL27BCTRL3);
116 writel(tmp, sc_base + SC_VPLL27BCTRL3);
119 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
120 tmp = readl(sc_base + SC_VPLL27ACTRL3);
122 writel(tmp, sc_base + SC_VPLL27ACTRL3);
123 tmp = readl(sc_base + SC_VPLL27BCTRL3);
125 writel(tmp, sc_base + SC_VPLL27BCTRL3);
130 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
131 tmp = readl(sc_base + SC_VPLL27ACTRL2);
133 writel(tmp, sc_base + SC_VPLL27ACTRL2);
134 tmp = readl(sc_base + SC_VPLL27BCTRL2);
136 writel(tmp, sc_base + SC_VPLL27BCTRL2);
138 /* set 0 to VPLA27WP and VPLA27WP */
139 tmp = readl(sc_base + SC_VPLL27ACTRL);
141 writel(tmp, sc_base + SC_VPLL27ACTRL);
142 tmp = readl(sc_base + SC_VPLL27BCTRL);
144 writel(tmp, sc_base + SC_VPLL27BCTRL);
147 void uniphier_ld4_pll_init(void)
151 uniphier_ld4_dpll_ssc_en();