arch/arm/mach-uniphier/clk/clk-dram-pro5.c

   1 /*
   2  * Copyright (C) 2015-2017 Socionext Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <linux/io.h>
   8
   9 #include "../init.h"
  10 #include "../sc-regs.h"
  11
  12 void uniphier_pro5_dram_clk_init(void)
  13 {
  14         u32 tmp;
  15
  16         /*
  17          * deassert reset
  18          * UMCA2: Ch1 (DDR3)
  19          * UMCA1, UMC31: Ch0 (WIO1)
  20          * UMCA0, UMC30: Ch0 (WIO0)
  21          */
  22         tmp = readl(SC_RSTCTRL4);
  23         tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
  24                SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
  25                SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
  26         writel(tmp, SC_RSTCTRL4);
  27         readl(SC_RSTCTRL4); /* dummy read */
  28
  29         /* provide clocks */
  30         tmp = readl(SC_CLKCTRL4);
  31         tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
  32                SC_CLKCTRL4_CEN_UMC0;
  33         writel(tmp, SC_CLKCTRL4);
  34         readl(SC_CLKCTRL4); /* dummy read */
  35 }