2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include "micro-support-card.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 static void uniphier_setup_xirq(void)
22 const void *fdt = gd->fdt_blob;
23 int soc_node, aidet_node;
25 unsigned long aidet_base;
28 soc_node = fdt_path_offset(fdt, "/soc");
32 aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
36 val = fdt_getprop(fdt, aidet_node, "reg", NULL);
40 aidet_base = fdt32_to_cpu(*val);
42 tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
43 tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
44 writel(tmp, aidet_base + 8);
46 tmp = readl(0x55000090); /* IRQCTL */
48 writel(tmp, 0x55000090);
51 #ifdef CONFIG_ARCH_UNIPHIER_LD11
52 static void uniphier_ld11_misc_init(void)
54 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
56 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
61 #ifdef CONFIG_ARCH_UNIPHIER_LD20
62 static void uniphier_ld20_misc_init(void)
64 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
66 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
69 /* ES1 errata: increase VDD09 supply to suppress VBO noise */
70 if (uniphier_get_soc_revision() == 1) {
71 writel(0x00000003, 0x6184e004);
72 writel(0x00000100, 0x6184e040);
73 writel(0x0000b500, 0x6184e024);
74 writel(0x00000001, 0x6184e000);
81 struct uniphier_initdata {
82 enum uniphier_soc_id soc_id;
84 void (*pll_init)(void);
85 void (*clk_init)(void);
86 void (*misc_init)(void);
89 struct uniphier_initdata uniphier_initdata[] = {
90 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
92 .soc_id = SOC_UNIPHIER_SLD3,
94 .pll_init = uniphier_sld3_pll_init,
95 .clk_init = uniphier_ld4_clk_init,
98 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
100 .soc_id = SOC_UNIPHIER_LD4,
102 .pll_init = uniphier_ld4_pll_init,
103 .clk_init = uniphier_ld4_clk_init,
106 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
108 .soc_id = SOC_UNIPHIER_PRO4,
110 .pll_init = uniphier_pro4_pll_init,
111 .clk_init = uniphier_pro4_clk_init,
114 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
116 .soc_id = SOC_UNIPHIER_SLD8,
118 .pll_init = uniphier_ld4_pll_init,
119 .clk_init = uniphier_ld4_clk_init,
122 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
124 .soc_id = SOC_UNIPHIER_PRO5,
126 .clk_init = uniphier_pro5_clk_init,
129 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
131 .soc_id = SOC_UNIPHIER_PXS2,
133 .clk_init = uniphier_pxs2_clk_init,
136 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
138 .soc_id = SOC_UNIPHIER_LD6B,
140 .clk_init = uniphier_pxs2_clk_init,
143 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
145 .soc_id = SOC_UNIPHIER_LD11,
147 .pll_init = uniphier_ld11_pll_init,
148 .clk_init = uniphier_ld11_clk_init,
149 .misc_init = uniphier_ld11_misc_init,
152 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
154 .soc_id = SOC_UNIPHIER_LD20,
156 .pll_init = uniphier_ld20_pll_init,
157 .misc_init = uniphier_ld20_misc_init,
162 static struct uniphier_initdata *uniphier_get_initdata(
163 enum uniphier_soc_id soc_id)
167 for (i = 0; i < ARRAY_SIZE(uniphier_initdata); i++) {
168 if (uniphier_initdata[i].soc_id == soc_id)
169 return &uniphier_initdata[i];
177 struct uniphier_initdata *initdata;
178 enum uniphier_soc_id soc_id;
183 soc_id = uniphier_get_soc_type();
184 initdata = uniphier_get_initdata(soc_id);
186 pr_err("unsupported board\n");
190 if (IS_ENABLED(CONFIG_NAND_DENALI)) {
191 ret = uniphier_pin_init(initdata->nand_2cs ?
192 "nand2cs_grp" : "nand_grp");
194 pr_err("failed to init NAND pins\n");
199 if (initdata->pll_init)
200 initdata->pll_init();
204 if (initdata->clk_init)
205 initdata->clk_init();
209 if (initdata->misc_init)
210 initdata->misc_init();
214 uniphier_setup_xirq();
218 support_card_late_init();
223 uniphier_smp_kick_all_cpus();