2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include "micro-support-card.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 static void uniphier_setup_xirq(void)
22 const void *fdt = gd->fdt_blob;
23 int soc_node, aidet_node;
25 unsigned long aidet_base;
28 soc_node = fdt_path_offset(fdt, "/soc");
32 aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
36 val = fdt_getprop(fdt, aidet_node, "reg", NULL);
40 aidet_base = fdt32_to_cpu(*val);
42 tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
43 tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
44 writel(tmp, aidet_base + 8);
46 tmp = readl(0x55000090); /* IRQCTL */
48 writel(tmp, 0x55000090);
51 static void uniphier_nand_pin_init(bool cs2)
53 #ifdef CONFIG_NAND_DENALI
54 if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp"))
55 pr_err("failed to init NAND pins\n");
61 const struct uniphier_board_data *bd;
65 bd = uniphier_get_board_param();
69 switch (uniphier_get_soc_type()) {
70 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
71 case SOC_UNIPHIER_SLD3:
72 uniphier_nand_pin_init(true);
74 uniphier_sld3_pll_init();
75 uniphier_ld4_clk_init();
78 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
79 case SOC_UNIPHIER_LD4:
80 uniphier_nand_pin_init(true);
82 uniphier_ld4_pll_init();
83 uniphier_ld4_clk_init();
86 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
87 case SOC_UNIPHIER_PRO4:
88 uniphier_nand_pin_init(false);
90 uniphier_pro4_pll_init();
91 uniphier_pro4_clk_init();
94 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
95 case SOC_UNIPHIER_SLD8:
96 uniphier_nand_pin_init(true);
98 uniphier_ld4_pll_init();
99 uniphier_ld4_clk_init();
102 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
103 case SOC_UNIPHIER_PRO5:
104 uniphier_nand_pin_init(true);
106 uniphier_pro5_clk_init();
109 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
110 case SOC_UNIPHIER_PXS2:
111 uniphier_nand_pin_init(true);
113 uniphier_pxs2_clk_init();
116 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
117 case SOC_UNIPHIER_LD6B:
118 uniphier_nand_pin_init(true);
120 uniphier_pxs2_clk_init();
123 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
124 case SOC_UNIPHIER_LD11:
125 uniphier_nand_pin_init(false);
126 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
128 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
131 uniphier_ld11_pll_init();
132 uniphier_ld11_clk_init();
135 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
136 case SOC_UNIPHIER_LD20:
137 /* ES1 errata: increase VDD09 supply to suppress VBO noise */
138 if (uniphier_get_soc_revision() == 1) {
139 writel(0x00000003, 0x6184e004);
140 writel(0x00000100, 0x6184e040);
141 writel(0x0000b500, 0x6184e024);
142 writel(0x00000001, 0x6184e000);
144 uniphier_nand_pin_init(false);
145 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
147 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
150 uniphier_ld20_pll_init(bd);
151 uniphier_ld20_clk_init();
159 uniphier_setup_xirq();
163 support_card_late_init();
168 uniphier_smp_kick_all_cpus();