arch/arm/mach-uniphier/arm64/arm-cci500.c

   1 /*
   2  * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
   3  *
   4  * Copyright (C) 2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <linux/bitops.h>
  11 #include <linux/io.h>
  12 #include <linux/sizes.h>
  13
  14 #define CCI500_BASE                     0x5FD00000
  15 #define CCI500_SLAVE_OFFSET             0x1000
  16
  17 #define CCI500_SNOOP_CTRL
  18 #define   CCI500_SNOOP_CTRL_EN_DVM      BIT(1)
  19 #define   CCI500_SNOOP_CTRL_EN_SNOOP    BIT(0)
  20
  21 void cci500_init(unsigned int nr_slaves)
  22 {
  23         unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
  24         int i;
  25
  26         for (i = 0; i < nr_slaves; i++) {
  27                 void __iomem *base;
  28                 u32 tmp;
  29
  30                 base = ioremap(slave_base, SZ_4K);
  31
  32                 tmp = readl(base);
  33                 tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
  34                 writel(tmp, base);
  35
  36                 iounmap(base);
  37
  38                 slave_base += CCI500_SLAVE_OFFSET;
  39         }
  40 }