1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
10 #include <linux/bitops.h>
11 #include <linux/delay.h>
13 #include <linux/kernel.h>
14 #include <linux/printk.h>
15 #include <linux/psci.h>
16 #include <linux/sizes.h>
17 #include <asm/processor.h>
19 #include <asm/secure.h>
22 #include "../soc-info.h"
23 #include "arm-mpcore.h"
24 #include "cache-uniphier.h"
26 #define UNIPHIER_SMPCTRL_ROM_RSV2 0x59801208
28 void uniphier_smp_trampoline(void);
29 void uniphier_smp_trampoline_end(void);
30 u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
32 static int uniphier_get_nr_cpus(void)
34 switch (uniphier_get_soc_id()) {
35 case UNIPHIER_PRO4_ID:
36 case UNIPHIER_PRO5_ID:
38 case UNIPHIER_PXS2_ID:
39 case UNIPHIER_LD6B_ID:
46 static void uniphier_smp_kick_all_cpus(void)
48 const u32 target_ways = BIT(0);
50 u32 trmp_src = (unsigned long)uniphier_smp_trampoline;
51 u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end;
52 u32 trmp_dest, trmp_dest_end;
56 nr_cpus = uniphier_get_nr_cpus();
60 for (i = 0; i < nr_cpus; i++) /* lock ways for all CPUs */
61 uniphier_cache_set_active_ways(i, 0);
62 uniphier_cache_inv_way(target_ways);
63 uniphier_cache_enable();
65 /* copy trampoline code */
66 uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways);
68 trmp_size = trmp_src_end - trmp_src;
70 trmp_dest = trmp_src & (SZ_64K - 1);
71 trmp_dest += SZ_1M - SZ_64K * 2;
73 trmp_dest_end = trmp_dest + trmp_size;
75 uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways);
77 writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2);
79 asm("dsb ishst\n" /* Ensure the write to ROM_RSV2 is visible */
80 "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
85 for (i = 1; i < nr_cpus; i++)
86 if (!uniphier_smp_booted[i])
92 /* barrier here because uniphier_smp_booted[] may be updated */
97 pr_warn("warning: some of secondary CPUs may not boot\n");
99 uniphier_cache_disable();
102 void psci_board_init(void)
104 unsigned long scu_base;
107 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base));
109 scu_ctrl = readl(scu_base + 0x30);
111 writel(scu_ctrl | 0x1, scu_base + 0x30);
113 scu_ctrl = readl(scu_base + SCU_CTRL);
114 scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE;
115 writel(scu_ctrl, scu_base + SCU_CTRL);
117 tmp = readl(scu_base + SCU_SNSAC);
119 writel(tmp, scu_base + SCU_SNSAC);
121 uniphier_smp_kick_all_cpus();
124 void psci_arch_init(void)
128 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
129 actlr |= 0x41; /* set SMP and FW bits */
130 asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
133 u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
135 s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
138 u32 cpu = cpuid & 0xff;
140 debug_puts("[U-Boot PSCI] psci_cpu_on: cpuid=");
142 debug_puts(", entry_point=");
143 debug_puth(entry_point);
144 debug_puts(", context_id=");
145 debug_puth(context_id);
148 psci_save(cpu, entry_point, context_id);
150 /* We assume D-cache is off, so do not call flush_dcache() here */
151 uniphier_psci_holding_pen_release = cpu;
153 /* Send an event to wake up the secondary CPU. */
157 return PSCI_RET_SUCCESS;
160 void __secure psci_system_reset(void)