2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/linkage.h>
11 #include <linux/sizes.h>
12 #include <asm/system.h>
15 mov r8, lr @ persevere link reg across call
18 * The UniPhier Boot ROM loads SPL code to the L2 cache.
19 * But CPUs can only do instruction fetch now because start.S has
20 * cleared C and M bits.
21 * First we need to turn on MMU and Dcache again to get back
24 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
25 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
26 mcr p15, 0, r0, c1, c0, 0
28 bl setup_init_ram @ RAM area for stack and page table
31 * Now we are using the page table embedded in the Boot ROM.
32 * It is not handy since it is not a straight mapped table for sLD3.
33 * Also, the access to the external bus is prohibited. What we need
34 * to do next is to create a page table and switch over to it.
37 bl __v7_flush_dcache_all
39 /* Disable MMU and Dcache before switching Page Table */
40 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
41 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
42 mcr p15, 0, r0, c1, c0, 0
46 #ifdef CONFIG_DEBUG_LL
50 mov lr, r8 @ restore link
51 mov pc, lr @ back to my caller
52 ENDPROC(lowlevel_init)
55 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
57 orr r0, r0, #0x20 @ disable TTBR1
58 mcr p15, 0, r0, c2, c0, 2
60 orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
61 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
64 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
66 mov r0, #-1 @ manager for all domains (No permission check)
67 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
73 * TLBs was already invalidated in "../start.S"
74 * So, we don't need to invalidate it here.
76 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
77 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
78 mcr p15, 0, r0, c1, c0, 0
84 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
85 * It is large enough for tmp RAM.
87 #define BOOT_RAM_SIZE (SZ_32K)
88 #define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
89 #define BOOT_RAM_WAYS (0x00000100) @ way 8
91 #define SSCO_BASE 0x506c0000
97 #define SSCOPPQSEF 0x25c
98 #define SSCOLPQS 0x260
100 ENTRY(setup_init_ram)
102 mrc p15, 0, r0, c2, c0, 0 @ TTBR0
103 ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
105 cmp r0, #0x50000000 @ is sLD3 page table?
106 biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1*******
108 /* Touch to zero for the boot way */
109 0: ldr r0, = 0x00408006 @ touch to zero with address range
110 str r0, [r1, #SSCOQM]
111 ldr r0, = BOOT_RAM_BASE
112 str r0, [r1, #SSCOQAD]
113 ldr r0, = BOOT_RAM_SIZE
114 str r0, [r1, #SSCOQSZ]
115 ldr r0, = BOOT_RAM_WAYS
116 str r0, [r1, #SSCOQWN]
117 ldr r0, [r1, #SSCOPPQSEF]
118 cmp r0, #0 @ check if the command is successfully set
119 bne 0b @ try again if an error occurs
121 1: ldr r0, [r1, #SSCOLPQS]
123 bne 1b @ wait until the operation is completed
124 str r0, [r1, #SSCOLPQS] @ clear the complete notification flag
127 ENDPROC(setup_init_ram)
129 #define DEVICE 0x00002002 /* Non-shareable Device */
130 #define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
132 ENTRY(create_page_table)
134 ldr r1, = BOOT_RAM_BASE
135 mov r12, r1 @ r12 is preserved during D-cache flush
136 0: str r0, [r1], #4 @ specify all the sections as Device
137 adds r0, r0, #0x00100000
141 str r0, [r12] @ mark the first section as Normal
142 add r0, r0, #0x00100000
143 str r0, [r12, #4] @ mark the second section as Normal
145 ENDPROC(create_page_table)