1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * On-chip UART initializaion for low-level debugging
5 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <linux/serial_reg.h>
9 #include <linux/linkage.h>
11 #include "../bcu/bcu-regs.h"
12 #include "../sc-regs.h"
13 #include "../sg-regs.h"
15 #if !defined(CONFIG_DEBUG_SEMIHOSTING)
16 #include CONFIG_DEBUG_LL_INCLUDE
19 #define SG_REVISION_TYPE_SHIFT 16
20 #define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
21 #define BAUDRATE 115200
22 #define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
24 .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
25 ldr \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
27 and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
28 orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
33 ldr r0, =(SG_BASE + SG_REVISION)
35 and r1, r1, #SG_REVISION_TYPE_MASK
36 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
38 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
39 #define UNIPHIER_LD4_UART_CLK 36864000
43 ldr r0, =(SG_BASE + SG_IECTRL)
48 sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
50 ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
55 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
56 #define UNIPHIER_PRO4_UART_CLK 73728000
60 sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
62 ldr r0, =(SG_BASE + SG_LOADPINCTRL)
66 ldr r0, =(SC_BASE + SC_CLKCTRL)
68 orr r1, r1, #SC_CLKCTRL_CEN_PERI
71 ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
76 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
77 #define UNIPHIER_SLD8_UART_CLK 80000000
81 ldr r0, =(SG_BASE + SG_IECTRL)
86 sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
88 ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
93 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
94 #define UNIPHIER_PRO5_UART_CLK 73728000
98 sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
99 sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
100 sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
101 sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
103 ldr r0, =(SG_BASE + SG_LOADPINCTRL)
107 ldr r0, =(SC_BASE + SC_CLKCTRL)
109 orr r1, r1, #SC_CLKCTRL_CEN_PERI
112 ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
117 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
118 #define UNIPHIER_PXS2_UART_CLK 88900000
122 ldr r0, =(SG_BASE + SG_IECTRL)
127 sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
128 sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
129 sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
130 sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
132 ldr r0, =(SC_BASE + SC_CLKCTRL)
134 orr r1, r1, #SC_CLKCTRL_CEN_PERI
137 ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
142 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
143 #define UNIPHIER_LD6B_UART_CLK 88900000
147 ldr r0, =(SG_BASE + SG_IECTRL)
152 sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
153 sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
154 sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
156 ldr r0, =(SC_BASE + SC_CLKCTRL)
158 orr r1, r1, #SC_CLKCTRL_CEN_PERI
161 ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
170 mov r1, #UART_LCR_WLEN8 << 8
175 ENDPROC(debug_ll_init)