1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
6 #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
7 #define _TEGRA_XUSB_PADCTL_COMMON_H_
11 #include <dm/ofnode.h>
14 #include <asm/arch-tegra/xusb-padctl.h>
15 #include <linux/ioport.h>
17 struct tegra_xusb_padctl_lane {
25 const unsigned int *funcs;
26 unsigned int num_funcs;
29 struct tegra_xusb_phy_ops {
30 int (*prepare)(struct tegra_xusb_phy *phy);
31 int (*enable)(struct tegra_xusb_phy *phy);
32 int (*disable)(struct tegra_xusb_phy *phy);
33 int (*unprepare)(struct tegra_xusb_phy *phy);
36 struct tegra_xusb_phy {
38 const struct tegra_xusb_phy_ops *ops;
39 struct tegra_xusb_padctl *padctl;
42 struct tegra_xusb_padctl_pin {
43 const struct tegra_xusb_padctl_lane *lane;
52 struct tegra_xusb_padctl_group {
55 const char *pins[MAX_PINS];
56 unsigned int num_pins;
62 struct tegra_xusb_padctl_soc {
63 const struct tegra_xusb_padctl_lane *lanes;
64 unsigned int num_lanes;
65 const char *const *functions;
66 unsigned int num_functions;
67 struct tegra_xusb_phy *phys;
68 unsigned int num_phys;
71 struct tegra_xusb_padctl_config {
74 struct tegra_xusb_padctl_group groups[MAX_GROUPS];
75 unsigned int num_groups;
78 struct tegra_xusb_padctl {
79 const struct tegra_xusb_padctl_soc *socdata;
80 struct tegra_xusb_padctl_config config;
85 extern struct tegra_xusb_padctl padctl;
87 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
90 return readl(padctl->regs.start + offset);
93 static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
94 u32 value, unsigned long offset)
96 writel(value, padctl->regs.start + offset);
99 int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
100 const struct tegra_xusb_padctl_soc *socdata);