2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
12 #include "xusb-padctl-common.h"
14 #include <asm/arch/clock.h>
16 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
18 if (phy && phy->ops && phy->ops->prepare)
19 return phy->ops->prepare(phy);
21 return phy ? -ENOSYS : -EINVAL;
24 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
26 if (phy && phy->ops && phy->ops->enable)
27 return phy->ops->enable(phy);
29 return phy ? -ENOSYS : -EINVAL;
32 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
34 if (phy && phy->ops && phy->ops->disable)
35 return phy->ops->disable(phy);
37 return phy ? -ENOSYS : -EINVAL;
40 int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
42 if (phy && phy->ops && phy->ops->unprepare)
43 return phy->ops->unprepare(phy);
45 return phy ? -ENOSYS : -EINVAL;
48 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
50 struct tegra_xusb_phy *phy;
53 for (i = 0; i < padctl.socdata->num_phys; i++) {
54 phy = &padctl.socdata->phys[i];
55 if (phy->type != type)
63 static const struct tegra_xusb_padctl_lane *
64 tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
68 for (i = 0; i < padctl->socdata->num_lanes; i++)
69 if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
70 return &padctl->socdata->lanes[i];
76 tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
77 struct tegra_xusb_padctl_group *group,
78 const void *fdt, int node)
83 group->name = fdt_get_name(fdt, node, &len);
85 len = fdt_count_strings(fdt, node, "nvidia,lanes");
87 error("failed to parse \"nvidia,lanes\" property");
91 group->num_pins = len;
93 for (i = 0; i < group->num_pins; i++) {
94 err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
97 error("failed to read string from \"nvidia,lanes\" property");
102 group->num_pins = len;
104 err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
106 error("failed to parse \"nvidia,func\" property");
110 group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
115 static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
120 for (i = 0; i < padctl->socdata->num_functions; i++)
121 if (strcmp(name, padctl->socdata->functions[i]) == 0)
128 tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
129 const struct tegra_xusb_padctl_lane *lane,
135 func = tegra_xusb_padctl_find_function(padctl, name);
139 for (i = 0; i < lane->num_funcs; i++)
140 if (lane->funcs[i] == func)
147 tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
148 const struct tegra_xusb_padctl_group *group)
152 for (i = 0; i < group->num_pins; i++) {
153 const struct tegra_xusb_padctl_lane *lane;
157 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
159 error("no lane for pin %s", group->pins[i]);
163 func = tegra_xusb_padctl_lane_find_function(padctl, lane,
166 error("function %s invalid for lane %s: %d",
167 group->func, lane->name, func);
171 value = padctl_readl(padctl, lane->offset);
173 /* set pin function */
174 value &= ~(lane->mask << lane->shift);
175 value |= func << lane->shift;
178 * Set IDDQ if supported on the lane and specified in the
181 if (lane->iddq > 0 && group->iddq >= 0) {
182 if (group->iddq != 0)
183 value &= ~(1 << lane->iddq);
185 value |= 1 << lane->iddq;
188 padctl_writel(padctl, value, lane->offset);
195 tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
196 struct tegra_xusb_padctl_config *config)
200 for (i = 0; i < config->num_groups; i++) {
201 const struct tegra_xusb_padctl_group *group;
204 group = &config->groups[i];
206 err = tegra_xusb_padctl_group_apply(padctl, group);
208 error("failed to apply group %s: %d",
218 tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
219 struct tegra_xusb_padctl_config *config,
220 const void *fdt, int node)
224 config->name = fdt_get_name(fdt, node, NULL);
226 fdt_for_each_subnode(fdt, subnode, node) {
227 struct tegra_xusb_padctl_group *group;
230 group = &config->groups[config->num_groups];
232 err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
235 error("failed to parse group %s", group->name);
239 config->num_groups++;
245 static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
246 const void *fdt, int node)
250 err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
252 error("registers not found");
256 fdt_for_each_subnode(fdt, subnode, node) {
257 struct tegra_xusb_padctl_config *config = &padctl->config;
259 err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
262 error("failed to parse entry %s: %d",
271 struct tegra_xusb_padctl padctl;
273 int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
274 const struct tegra_xusb_padctl_soc *socdata)
279 for (i = 0; i < count; i++) {
280 if (!fdtdec_get_is_enabled(fdt, nodes[i]))
283 padctl.socdata = socdata;
285 err = tegra_xusb_padctl_parse_dt(&padctl, fdt, nodes[i]);
287 error("failed to parse DT: %d", err);
291 /* deassert XUSB padctl reset */
292 reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
294 err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
296 error("failed to apply pinmux: %d", err);
300 /* only a single instance is supported */