2 * (C) Copyright 2013-2015
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra210 Clock control functions */
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sysctr.h>
14 #include <asm/arch/tegra.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra210 has muxes for the
22 * peripheral clocks, and in most cases there are four options for the clock
23 * source. This gives us a clock 'type' and exploits what commonality exists
26 * Letters are obvious, except for T which means CLK_M, and S which means the
27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
28 * datasheet) and PLL_M are different things. The former is the basic
29 * clock supplied to the SOC from an external oscillator. The latter is the
32 * See definitions in clock_id in the header file.
35 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
36 CLOCK_TYPE_MCPA, /* and so on */
49 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
52 CLOCK_TYPE_MCPTM2C2C3,
54 CLOCK_TYPE_AC2CC3P_TS2,
55 CLOCK_TYPE_PC01C00_C42C41TC40,
58 CLOCK_TYPE_NONE = -1, /* invalid clock type */
62 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
66 * Clock source mux for each clock type. This just converts our enum into
67 * a list of mux sources for use by the code.
70 * The extra column in each clock source array is used to store the mask
71 * bits in its register for the source.
73 #define CLK(x) CLOCK_ID_ ## x
74 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
75 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
76 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
78 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
79 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
81 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
82 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
84 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
85 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
87 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
88 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
90 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
91 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
93 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
94 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
96 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
97 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
99 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
100 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
102 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
103 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
106 /* Additional clock types on Tegra114+ */
107 /* CLOCK_TYPE_PC2CC3M */
108 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
109 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
111 /* CLOCK_TYPE_PC2CC3S_T */
112 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
113 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
115 /* CLOCK_TYPE_PC2CC3M_T */
116 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
117 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
119 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
120 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
121 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
123 /* CLOCK_TYPE_MC2CC3P_A */
124 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
125 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
128 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
129 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
131 /* CLOCK_TYPE_MCPTM2C2C3 */
132 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
133 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
135 /* CLOCK_TYPE_PC2CC3T_S */
136 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
137 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
139 /* CLOCK_TYPE_AC2CC3P_TS2 */
140 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
141 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
143 /* CLOCK_TYPE_PC01C00_C42C41TC40 */
144 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
145 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
150 * Clock type for each peripheral clock source. We put the name in each
151 * record just so it is easy to match things up
153 #define TYPE(name, type) type
154 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
156 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
157 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
158 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
159 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
160 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
161 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
162 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
163 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
166 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
167 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
168 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
169 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
170 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
171 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
172 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
173 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
176 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
177 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
178 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
179 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
180 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
181 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
182 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
183 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
186 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
187 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
188 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
189 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
190 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
191 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
192 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
193 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
196 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
197 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
198 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
199 TYPE(PERIPHC_23h, CLOCK_TYPE_NONE),
200 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
201 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
202 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
203 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
206 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
207 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
208 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
209 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
212 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
213 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
216 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
217 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
218 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
219 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
220 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
221 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
222 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
223 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
226 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
227 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
228 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
229 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
230 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
231 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
232 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
233 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
236 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
237 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
238 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
239 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
240 TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT),
241 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
242 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
243 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
246 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
247 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
248 TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE),
249 TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE),
250 TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE),
251 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
252 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
253 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
256 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
257 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
258 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
259 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
260 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
261 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
262 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
263 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
266 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
267 TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
268 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
269 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
270 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
271 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
272 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
273 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
276 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
277 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
278 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
279 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
280 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
281 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
282 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
283 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
286 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
287 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
288 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
289 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
290 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
291 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
292 TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE),
293 TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE),
296 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
297 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
298 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
299 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
300 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
301 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
302 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
303 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
306 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
307 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
308 TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE),
309 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
310 TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE),
311 TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE),
312 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
313 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
316 TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE),
317 TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE),
318 TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE),
319 TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE),
320 TYPE(PERIPHC_84h, CLOCK_TYPE_NONE),
321 TYPE(PERIPHC_85h, CLOCK_TYPE_NONE),
322 TYPE(PERIPHC_86h, CLOCK_TYPE_NONE),
323 TYPE(PERIPHC_87h, CLOCK_TYPE_NONE),
326 TYPE(PERIPHC_88h, CLOCK_TYPE_NONE),
327 TYPE(PERIPHC_89h, CLOCK_TYPE_NONE),
328 TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
329 TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
330 TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
331 TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE),
332 TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
333 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
336 TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE),
337 TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE),
341 * This array translates a periph_id to a periphc_internal_id
343 * Not present/matched up:
344 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
345 * SPDIF - which is both 0x08 and 0x0c
348 #define NONE(name) (-1)
349 #define OFFSET(name, value) PERIPHC_ ## name
350 #define INTERNAL_ID(id) (id & 0x000000ff)
351 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
360 PERIPHC_UART2, /* and vfir 0x68 */
392 /* Middle word: 63:32 */
404 PERIPHC_SBC1, /* SBCx = SPIx */
432 /* Upper word 95:64 */
592 /* Y: 192 (192 - 223) */
594 PERIPHC_SDMMC_LEGACY_TM,
598 PERIPHC_DMIC3, /* 197 */
599 PERIPHC_APE, /* 198 */
613 PERIPHC_VI_I2C, /* 208 */
616 PERIPHC_QSPI, /* 211 */
626 PERIPHC_NVENC, /* 219 */
634 * Get the oscillator frequency, from the corresponding hardware configuration
635 * field. Note that Tegra30+ support 3 new higher freqs, but we map back
636 * to the old T20 freqs. Support for the higher oscillators is TBD.
638 enum clock_osc_freq clock_get_osc_freq(void)
640 struct clk_rst_ctlr *clkrst =
641 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
644 reg = readl(&clkrst->crc_osc_ctrl);
645 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
647 * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
648 * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
651 debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
652 /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
657 * Map to most common (T20) freqs (except 38.4, handled above):
658 * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
663 /* Returns a pointer to the clock source register for a peripheral */
664 u32 *get_periph_source_reg(enum periph_id periph_id)
666 struct clk_rst_ctlr *clkrst =
667 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
668 enum periphc_internal_id internal_id;
670 /* Coresight is a special case */
671 if (periph_id == PERIPH_ID_CSI)
672 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
674 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
675 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
676 assert(internal_id != -1);
678 if (internal_id < PERIPHC_VW_FIRST)
680 return &clkrst->crc_clk_src[internal_id];
682 if (internal_id < PERIPHC_X_FIRST) {
684 internal_id -= PERIPHC_VW_FIRST;
685 return &clkrst->crc_clk_src_vw[internal_id];
688 if (internal_id < PERIPHC_Y_FIRST) {
690 internal_id -= PERIPHC_X_FIRST;
691 return &clkrst->crc_clk_src_x[internal_id];
695 internal_id -= PERIPHC_Y_FIRST;
696 return &clkrst->crc_clk_src_y[internal_id];
700 * Given a peripheral ID and the required source clock, this returns which
701 * value should be programmed into the source mux for that peripheral.
703 * There is special code here to handle the one source type with 5 sources.
705 * @param periph_id peripheral to start
706 * @param source PLL id of required parent clock
707 * @param mux_bits Set to number of bits in mux register: 2 or 4
708 * @param divider_bits Set to number of divider bits (8 or 16)
709 * @return mux value (0-4, or -1 if not found)
711 int get_periph_clock_source(enum periph_id periph_id,
712 enum clock_id parent, int *mux_bits, int *divider_bits)
714 enum clock_type_id type;
715 enum periphc_internal_id internal_id;
718 assert(clock_periph_id_isvalid(periph_id));
720 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
721 assert(periphc_internal_id_isvalid(internal_id));
723 type = clock_periph_type[internal_id];
724 assert(clock_type_id_isvalid(type));
726 *mux_bits = clock_source[type][CLOCK_MAX_MUX];
728 if (type == CLOCK_TYPE_PC2CC3M_T16)
733 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
734 if (clock_source[type][mux] == parent)
737 /* if we get here, either us or the caller has made a mistake */
738 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
743 void clock_set_enable(enum periph_id periph_id, int enable)
745 struct clk_rst_ctlr *clkrst =
746 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
750 /* Enable/disable the clock to this peripheral */
751 assert(clock_periph_id_isvalid(periph_id));
752 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
753 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
754 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
755 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
756 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
757 clk = &clkrst->crc_clk_out_enb_x;
759 clk = &clkrst->crc_clk_out_enb_y;
763 reg |= PERIPH_MASK(periph_id);
765 reg &= ~PERIPH_MASK(periph_id);
769 void reset_set_enable(enum periph_id periph_id, int enable)
771 struct clk_rst_ctlr *clkrst =
772 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
776 /* Enable/disable reset to the peripheral */
777 assert(clock_periph_id_isvalid(periph_id));
778 if (periph_id < PERIPH_ID_VW_FIRST)
779 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
780 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
781 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
782 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
783 reset = &clkrst->crc_rst_devices_x;
785 reset = &clkrst->crc_rst_devices_y;
789 reg |= PERIPH_MASK(periph_id);
791 reg &= ~PERIPH_MASK(periph_id);
795 #ifdef CONFIG_OF_CONTROL
797 * Convert a device tree clock ID to our peripheral ID. They are mostly
798 * the same but we are very cautious so we check that a valid clock ID is
801 * @param clk_id Clock ID according to tegra210 device tree binding
802 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
804 enum periph_id clk_id_to_periph_id(int clk_id)
806 if (clk_id > PERIPH_ID_COUNT)
807 return PERIPH_ID_NONE;
810 case PERIPH_ID_RESERVED4:
811 case PERIPH_ID_RESERVED25:
812 case PERIPH_ID_RESERVED35:
813 case PERIPH_ID_RESERVED36:
814 case PERIPH_ID_RESERVED38:
815 case PERIPH_ID_RESERVED43:
816 case PERIPH_ID_RESERVED49:
817 case PERIPH_ID_RESERVED53:
818 case PERIPH_ID_RESERVED64:
819 case PERIPH_ID_RESERVED84:
820 case PERIPH_ID_RESERVED85:
821 case PERIPH_ID_RESERVED86:
822 case PERIPH_ID_RESERVED88:
823 case PERIPH_ID_RESERVED90:
824 case PERIPH_ID_RESERVED92:
825 case PERIPH_ID_RESERVED93:
826 case PERIPH_ID_RESERVED94:
827 case PERIPH_ID_V_RESERVED2:
828 case PERIPH_ID_V_RESERVED4:
829 case PERIPH_ID_V_RESERVED17:
830 case PERIPH_ID_V_RESERVED18:
831 case PERIPH_ID_V_RESERVED19:
832 case PERIPH_ID_V_RESERVED20:
833 case PERIPH_ID_V_RESERVED21:
834 case PERIPH_ID_V_RESERVED22:
835 case PERIPH_ID_W_RESERVED2:
836 case PERIPH_ID_W_RESERVED3:
837 case PERIPH_ID_W_RESERVED4:
838 case PERIPH_ID_W_RESERVED5:
839 case PERIPH_ID_W_RESERVED6:
840 case PERIPH_ID_W_RESERVED7:
841 case PERIPH_ID_W_RESERVED9:
842 case PERIPH_ID_W_RESERVED10:
843 case PERIPH_ID_W_RESERVED11:
844 case PERIPH_ID_W_RESERVED12:
845 case PERIPH_ID_W_RESERVED13:
846 case PERIPH_ID_W_RESERVED15:
847 case PERIPH_ID_W_RESERVED16:
848 case PERIPH_ID_W_RESERVED17:
849 case PERIPH_ID_W_RESERVED18:
850 case PERIPH_ID_W_RESERVED19:
851 case PERIPH_ID_W_RESERVED20:
852 case PERIPH_ID_W_RESERVED23:
853 case PERIPH_ID_W_RESERVED29:
854 case PERIPH_ID_W_RESERVED30:
855 case PERIPH_ID_W_RESERVED31:
856 return PERIPH_ID_NONE;
861 #endif /* CONFIG_OF_CONTROL */
864 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
865 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
867 void tegra210_setup_pllp(void)
869 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
872 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
875 /* Assert RSTN before enable */
876 reg = PLLP_OUT1_RSTN_EN;
877 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
878 /* Set divisor and reenable */
879 reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
880 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
881 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
884 /* Assert RSTN before enable */
885 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
886 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
887 /* Set divisor and reenable */
888 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
889 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
890 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
891 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
892 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
895 * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
896 * you can change PLLP_BASE DIVP here. Currently defaults
897 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
898 * See Table 13 in section 5.1.4 in T210 TRM for more info.
902 void clock_early_init(void)
904 struct clk_rst_ctlr *clkrst =
905 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
908 tegra210_setup_pllp();
911 * PLLC output frequency set to 600Mhz
912 * PLLD output frequency set to 925Mhz
914 switch (clock_get_osc_freq()) {
915 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
916 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
917 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
920 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
921 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
922 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
925 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
926 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
927 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
929 case CLOCK_OSC_FREQ_19_2:
930 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
931 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
933 case CLOCK_OSC_FREQ_38_4:
934 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0);
935 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0);
939 * These are not supported. It is too early to print a
940 * message and the UART likely won't work anyway due to the
941 * oscillator being wrong.
946 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
947 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,
952 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps
955 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],
959 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
960 data = (1 << PLLD_ENABLE_CLK) | (1 << PLLD_EN_LCKDET);
961 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
965 void arch_timer_init(void)
967 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
970 freq = clock_get_rate(CLOCK_ID_OSC);
971 debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
975 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
978 /* Only Tegra114+ has the System Counter regs */
979 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
980 writel(freq, &sysctr->cntfid0);
982 val = readl(&sysctr->cntcr);
983 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
984 writel(val, &sysctr->cntcr);
985 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
988 #define PLLE_SS_CNTL 0x68
989 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
990 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
991 #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
992 #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
993 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
994 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
995 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
996 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
998 #define PLLE_BASE 0x0e8
999 #define PLLE_BASE_ENABLE (1 << 30)
1000 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
1001 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
1002 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
1003 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
1005 #define PLLE_MISC 0x0ec
1006 #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
1007 #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
1008 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
1009 #define PLLE_MISC_PTS (1 << 8)
1010 #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
1011 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
1013 #define PLLE_AUX 0x48c
1014 #define PLLE_AUX_SEQ_ENABLE (1 << 24)
1015 #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
1017 int tegra_plle_enable(void)
1019 unsigned int m = 1, n = 200, cpcon = 13;
1022 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1023 value &= ~PLLE_BASE_LOCK_OVERRIDE;
1024 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1026 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
1027 value |= PLLE_AUX_ENABLE_SWCTL;
1028 value &= ~PLLE_AUX_SEQ_ENABLE;
1029 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
1033 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
1034 value |= PLLE_MISC_IDDQ_SWCTL;
1035 value &= ~PLLE_MISC_IDDQ_OVERRIDE;
1036 value |= PLLE_MISC_LOCK_ENABLE;
1037 value |= PLLE_MISC_PTS;
1038 value |= PLLE_MISC_VREG_BG_CTRL(3);
1039 value |= PLLE_MISC_VREG_CTRL(2);
1040 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
1044 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1045 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
1046 PLLE_SS_CNTL_BYPASS_SS;
1047 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1049 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1050 value &= ~PLLE_BASE_PLDIV_CML(0xf);
1051 value &= ~PLLE_BASE_NDIV(0xff);
1052 value &= ~PLLE_BASE_MDIV(0xff);
1053 value |= PLLE_BASE_PLDIV_CML(cpcon);
1054 value |= PLLE_BASE_NDIV(n);
1055 value |= PLLE_BASE_MDIV(m);
1056 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1060 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1061 value |= PLLE_BASE_ENABLE;
1062 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1067 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1068 value &= ~PLLE_SS_CNTL_SSCINVERT;
1069 value &= ~PLLE_SS_CNTL_SSCCENTER;
1071 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1072 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
1073 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
1075 value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
1076 value |= PLLE_SS_CNTL_SSCINC(0x01);
1077 value |= PLLE_SS_CNTL_SSCMAX(0x25);
1079 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1081 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1082 value &= ~PLLE_SS_CNTL_SSCBYP;
1083 value &= ~PLLE_SS_CNTL_BYPASS_SS;
1084 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1088 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1089 value &= ~PLLE_SS_CNTL_INTERP_RESET;
1090 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);