1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
8 #include <asm/arch/tegra.h>
9 #include <asm/arch-tegra/pmc.h>
12 static void enable_cpu_power_rail(void)
14 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
17 reg = readl(&pmc->pmc_cntrl);
19 writel(reg, &pmc->pmc_cntrl);
22 * The TI PMU65861C needs a 3.75ms delay between enabling
23 * the power rail and enabling the CPU clock. This delay
24 * between SM1EN and SM1 is for switching time + the ramp
25 * up of the voltage to the CPU (VDD_CPU from PMU).
30 void start_cpu(u32 reset_vector)
33 enable_cpu_power_rail();
35 /* Hold the CPUs in reset */
38 /* Disable the CPU clock */
41 /* Enable CoreSight */
42 clock_enable_coresight(1);
45 * Set the entry point for CPU execution from reset,
46 * if it's a non-zero value.
49 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
51 /* Enable the CPU clock */
54 /* If the CPU doesn't already have power, power it up */
57 /* Take the CPU out of reset */