2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
12 #include "../xusb-padctl-common.h"
14 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
16 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
17 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
18 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
19 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
21 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
22 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
23 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
24 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
26 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
27 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
29 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
31 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
32 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
33 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
34 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
35 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
36 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
38 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
39 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
40 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
42 enum tegra124_function {
52 static const char *const tegra124_functions[] = {
62 static const unsigned int tegra124_otg_functions[] = {
69 static const unsigned int tegra124_usb_functions[] = {
74 static const unsigned int tegra124_pci_functions[] = {
81 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
88 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
89 .funcs = tegra124_##_funcs##_functions, \
92 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
93 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
94 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
95 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
96 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
97 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
98 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
99 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
100 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
101 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
102 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
103 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
104 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
107 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
111 if (padctl->enable++ > 0)
114 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
115 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
116 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
120 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
121 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
122 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
126 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
127 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
128 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
133 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
137 if (padctl->enable == 0) {
138 error("unbalanced enable/disable");
142 if (--padctl->enable > 0)
145 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
146 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
147 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
151 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
152 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
153 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
157 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
158 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
159 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
164 static int phy_prepare(struct tegra_xusb_phy *phy)
166 return tegra_xusb_padctl_enable(phy->padctl);
169 static int phy_unprepare(struct tegra_xusb_phy *phy)
171 return tegra_xusb_padctl_disable(phy->padctl);
174 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
176 struct tegra_xusb_padctl *padctl = phy->padctl;
177 int err = -ETIMEDOUT;
181 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
182 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
183 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
185 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
186 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
187 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
188 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
189 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
191 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
192 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
193 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
195 start = get_timer(0);
197 while (get_timer(start) < 50) {
198 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
199 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
208 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
210 struct tegra_xusb_padctl *padctl = phy->padctl;
213 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
214 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
215 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
220 static int sata_phy_enable(struct tegra_xusb_phy *phy)
222 struct tegra_xusb_padctl *padctl = phy->padctl;
223 int err = -ETIMEDOUT;
227 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
228 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
229 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
230 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
232 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
233 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
234 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
235 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
237 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
238 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
239 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
241 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
242 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
243 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
245 start = get_timer(0);
247 while (get_timer(start) < 50) {
248 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
249 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
258 static int sata_phy_disable(struct tegra_xusb_phy *phy)
260 struct tegra_xusb_padctl *padctl = phy->padctl;
263 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
264 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
265 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
267 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
268 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
269 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
271 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
272 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
273 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
274 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
276 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
277 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
278 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
279 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
284 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
285 .prepare = phy_prepare,
286 .enable = pcie_phy_enable,
287 .disable = pcie_phy_disable,
288 .unprepare = phy_unprepare,
291 static const struct tegra_xusb_phy_ops sata_phy_ops = {
292 .prepare = phy_prepare,
293 .enable = sata_phy_enable,
294 .disable = sata_phy_disable,
295 .unprepare = phy_unprepare,
298 static struct tegra_xusb_phy tegra124_phys[] = {
300 .type = TEGRA_XUSB_PADCTL_PCIE,
301 .ops = &pcie_phy_ops,
305 .type = TEGRA_XUSB_PADCTL_SATA,
306 .ops = &sata_phy_ops,
311 static const struct tegra_xusb_padctl_soc tegra124_socdata = {
312 .lanes = tegra124_lanes,
313 .num_lanes = ARRAY_SIZE(tegra124_lanes),
314 .functions = tegra124_functions,
315 .num_functions = ARRAY_SIZE(tegra124_functions),
316 .phys = tegra124_phys,
317 .num_phys = ARRAY_SIZE(tegra124_phys),
320 void tegra_xusb_padctl_init(const void *fdt)
324 count = fdtdec_find_aliases_for_id(fdt, "padctl",
325 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
326 nodes, ARRAY_SIZE(nodes));
327 if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata))