1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
10 #include <asm/types.h>
12 #include <asm/arch/powergate.h>
13 #include <asm/arch/tegra.h>
15 #define PWRGATE_TOGGLE 0x30
16 #define PWRGATE_TOGGLE_START (1 << 8)
18 #define REMOVE_CLAMPING 0x34
20 #define PWRGATE_STATUS 0x38
22 static int tegra_powergate_set(enum tegra_powergate id, bool state)
24 u32 value, mask = state ? (1 << id) : 0, old_mask;
25 unsigned long start, timeout = 25;
27 value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
28 old_mask = value & (1 << id);
33 writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
37 while (get_timer(start) < timeout) {
38 value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
39 if ((value & (1 << id)) == mask)
46 int tegra_powergate_power_on(enum tegra_powergate id)
48 return tegra_powergate_set(id, true);
51 int tegra_powergate_power_off(enum tegra_powergate id)
53 return tegra_powergate_set(id, false);
56 static int tegra_powergate_remove_clamping(enum tegra_powergate id)
61 * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
62 * partitions reversed. This was originally introduced on Tegra20 but
63 * has since been carried forward for backwards-compatibility.
65 if (id == TEGRA_POWERGATE_VDEC)
66 value = 1 << TEGRA_POWERGATE_PCIE;
67 else if (id == TEGRA_POWERGATE_PCIE)
68 value = 1 << TEGRA_POWERGATE_VDEC;
72 writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
77 int tegra_powergate_sequence_power_up(enum tegra_powergate id,
78 enum periph_id periph)
82 reset_set_enable(periph, 1);
84 err = tegra_powergate_power_on(id);
92 err = tegra_powergate_remove_clamping(id);
98 reset_set_enable(periph, 0);